Cpu Interface - Renesas F-ZTAT H8 Series Hardware Manual

Bit 0—Reserved: Do not set to 1.
15.3

CPU Interface

ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 15.2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU
(H'AA)
Lower-byte read
CPU
(H'40)
Figure 15.2 A/D Data Register Access Operation (Reading H'AA40)
Bus interface
ADDRnH
(H'AA)
Bus interface
ADDRnH
(H'AA)
Section 15 A/D Converter
Module data bus
TEMP
(H'40)
ADDRnL
(H'40)
(n = A to D)
Module data bus
TEMP
(H'40)
ADDRnL
(H'40)
(n = A to D)
Rev. 3.00 Mar 21, 2006 page 529 of 814
REJ09B0302-0300