Renesas F-ZTAT H8 Series Hardware Manual page 312

Section 9 I/O Ports
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for pins PA
in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When
a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read.
Bit 7
PA
7
Initial value 0
Read/Write R/W
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Mar 21, 2006 page 284 of 814
REJ09B0302-0300
6 5 4
PA PA PA
6 5
0 0 0
R/W R/W R/W
Port A data 7 to 0
These bits store data for port A pins
3 2
PA PA
4 3 2
0 0
R/W R/W
to PA . When a bit
7 0
1 0
PA PA
1 0
0 0
R/W R/W