Renesas F-ZTAT H8 Series Hardware Manual page 237

Figure 8.2 illustrates how I/O mode operates.
Address T
Address B
Legend:
L = initial setting of MAR
N = initial setting of ETCR
Address T = L
Address B = L + (–1)
The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared and the transfer ends.
If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer count is
65,536, obtained by setting ETCR to H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, and
external request signals.
1 byte or word is
transferred per request
⋅ (2 ⋅ N – 1)
DTID DTSZ
Figure 8.2 Operation in I/O Mode
Transfer
Rev. 3.00 Mar 21, 2006 page 209 of 814
Section 8 DMA Controller
IOAR
REJ09B0302-0300