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19.5.3
Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time t
cyc
settings that give system clock frequencies less than 2 MHz.
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 20.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
in the AC electrical characteristics. Note that φ
Section 19 Clock Pulse Generator
= 2 MHz. Avoid
MIN
Rev. 3.00 Mar 21, 2006 page 615 of 814
REJ09B0302-0300
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