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8.2
Register Descriptions (Short Address Mode).................................................................... 191
8.2.1
Memory Address Registers (MAR) ..................................................................... 192
8.2.2
I/O Address Registers (IOAR) ............................................................................. 193
8.2.3
Execute Transfer Count Registers (ETCR).......................................................... 194
8.2.4
Data Transfer Control Registers (DTCR) ............................................................ 195
8.3
Register Descriptions (Full Address Mode)...................................................................... 198
8.3.1
Memory Address Registers (MAR) ..................................................................... 198
8.3.2
I/O Address Registers (IOAR) ............................................................................. 199
8.3.3
Execute Transfer Count Registers (ETCR).......................................................... 199
8.3.4
Data Transfer Control Registers (DTCR) ............................................................ 201
8.4
Operation........................................................................................................................... 206
8.4.1
Overview.............................................................................................................. 206
8.4.2
I/O Mode.............................................................................................................. 208
8.4.3
Idle Mode............................................................................................................. 210
8.4.4
Repeat Mode ........................................................................................................ 213
8.4.5
Normal Mode....................................................................................................... 217
8.4.6
Block Transfer Mode ........................................................................................... 220
8.4.7
DMAC Activation................................................................................................ 225
8.4.8
DMAC Bus Cycle ................................................................................................ 227
8.4.9
DMAC Multiple-Channel Operation ................................................................... 233
8.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 234
8.4.11 NMI Interrupts and DMAC.................................................................................. 235
8.4.12 Aborting a DMA Transfer.................................................................................... 236
8.4.13 Exiting Full Address Mode .................................................................................. 237
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 238
8.5
Interrupts ........................................................................................................................... 239
8.6
Usage Notes ...................................................................................................................... 240
8.6.1
Note on Word Data Transfer................................................................................ 240
8.6.2
DMAC Self-Access ............................................................................................. 240
8.6.3
Longword Access to Memory Address Registers ................................................ 240
8.6.4
Note on Full Address Mode Setup ....................................................................... 240
8.6.5
Note on Activating DMAC by Internal Interrupts ............................................... 240
8.6.6
NMI Interrupts and Block Transfer Mode ........................................................... 242
8.6.7
Memory and I/O Address Register Values .......................................................... 242
8.6.8
Bus Cycle when Transfer Is Aborted ................................................................... 243
9.1
Overview........................................................................................................................... 245
9.2
Port 1................................................................................................................................. 249
9.2.1
Overview.............................................................................................................. 249
.............................................................................................................. 245
Rev. 3.00 Mar 21, 2006 page xix of xxviii
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