Renesas F-ZTAT H8 Series Hardware Manual page 535

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Smart Card Mode Register (SCMR): If the smart card follows the direct convention, clear the

SDIR and SINV bits to 0. If the smart card follows the indirect convention, set the SDIR and

SINV bits to 1. To use the smart card interface, set the SMIF bit to 1.

The register settings and examples of starting character waveforms are shown below for two smart

cards, one following the direct convention and one the inverse convention.

• Direct convention (SDIR = SINV = O/E = 0)

In the direct convention, state Z corresponds to logic level 1, and state A to logic level 0.

Characters are transmitted and received LSB-first. In the example above the first character data

is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.

• Inverse convention (SDIR = SINV = O/E = 1)

In the inverse convention, state A corresponds to the logic level 1, and state Z to the logic level

0. Characters are transmitted and received MSB-first. In the example above the first character

data is H'3F. Following the even parity rule designated for smart cards, the parity bit logic

level is 0, corresponding to state Z.

In the H8/3052BF, the SINV bit inverts only the data bits D7 to D0. The parity bit is not inverted,

so the O/E bit in SMR must be set to odd parity mode. This applies in both transmitting and

Section 14 Smart Card Interface

Rev. 3.00 Mar 21, 2006 page 507 of 814

REJ09B0302-0300