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Appendix B Internal I/O Register
FLMCR1—Flash Memory Control Register 1
Bit
7
FWE
Initial value *
1
Read/Write
R
Flash write enable bit
0 When a low level is input to the FWE pin (hardware protection state)
1 When a high level is input to the FWE pin
Note: * The initial value is H'00 in modes 5, 6, and 7 (on-chip flash memory enabled). In modes 1, 2,
3, and 4 (on-chip flash memory disabled), this register cannot be modified and is always read
as H'FF.
Rev. 3.00 Mar 21, 2006 page 712 of 814
REJ09B0302-0300
6
5
SWE1
ESU1
0
0
R/W*
R/W*
Erase-verify mode 1
0 Erase-verify mode cleared
1 Transition to erase-verify mode
Program setup bit 1
0 Program setup cleared
1 Program setup
Erase setup bit 1
0 Erase setup cleared
1 Erase setup
Software write enable bit 1
0 Write disabled
(Initial value)
1 Write enabled
H'40
4
3
PSU1
EV1
PV1
0
0
R/W*
R/W*
R/W*
Program mode 1
0 Program mode cleared
1 Transition to program mode
Erase mode 1
0 Erase mode cleared
1 Transition to erase mode
Program-verify mode 1
0 Program-verify mode cleared
1 Transition to program-verify mode
(Initial value)
(Initial value)
Flash memory
2
1
0
E1
P1
0
0
0
R/W*
R/W*
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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