Renesas F-ZTAT H8 Series Hardware Manual page 394

Section 10 16-Bit Integrated Timer Unit (ITU)
TCNT4
T
T – 1
H'0000
H'FFFF
Figure 10.41 Changing a General Register Setting by Buffer Transfer (Caution 2)
 General register settings outside the counting range (H'0000 to GRA3)
Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to
a value outside the counting range. When a buffer register is set to a value outside the
counting range, then later restored to a value within the counting range, the counting
direction (up or down) must be the same both times.
GRA3
GR
H'0000
Output pin
Output pin
BR
GR
Write during down-counting
Figure 10.42 Changing a General Register Setting by Buffer Transfer (Example 2)
Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow
before writing to the buffer register. They can also be made by using GRA3 compare match
to activate the DMAC.
Rev. 3.00 Mar 21, 2006 page 366 of 814
REJ09B0302-0300
TCNT3
0% duty cycle 100% duty cycle
Write during up-counting
Illegal changes