Renesas F-ZTAT H8 Series Hardware Manual page 269

Yes
Interrupt handling
by CPU
Figure 8.26 Procedure for Enabling DMAC while On-Chip Supporting Module Is
If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected
activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for
example, the selected activating source cannot generate CPU interrupts. To terminate DMAC
operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue
DMAC operations, carry out steps 2 and 4 in figure 8.26 before and after setting the DTME bit to
1.
When an ITU interrupt activates the DMAC, make sure the next interrupt does not occur before
the DMA transfer ends. If one ITU interrupt activates two or more channels, make sure the next
interrupt does not occur before the DMA transfers end on all the activated channels. If the next
interrupt occurs before a transfer ends, the channel or channels for which that interrupt was
selected may fail to accept further activation requests.
Enabling of DMAC
Selected interrupt
requested?
No
Clear selected interrupt's
enable bit to 0
Enable DMAC
Set selected interrupt's
enable bit to 1
DMAC operates
Operating (Example)
Section 8 DMA Controller
1. While the DTE bit is cleared to
0, interrupt requests are sent
to the CPU.
2. Clear the interrupt enable bit to
0 in the interrupt-generating
1
on-chip supporting module.
3. Enable the DMAC.
4. Enable the DMAC-activating
interrupt.
2
3
4
Rev. 3.00 Mar 21, 2006 page 241 of 814
REJ09B0302-0300