Renesas F-ZTAT H8 Series Hardware Manual page 413

Contention between General Register Write and Compare Match: If a compare match occurs
in the T state of a general register write cycle, writing takes priority and the compare match signal
3
is inhibited. See figure 10.64.
φ
Address bus
Internal write signal
TCNT
GR
Compare match signal
Figure 10.64 Contention between General Register Write and Compare Match
Section 10 16-Bit Integrated Timer Unit (ITU)
General register write cycle
T T
1 2
GR address
N
N
General register write data
Rev. 3.00 Mar 21, 2006 page 385 of 814
T
3
N + 1
M
Inhibited
REJ09B0302-0300