Register Descriptions; A/D Data Registers A To D (Addra To Addrd) - Renesas F-ZTAT H8 Series Hardware Manual

15.2

Register Descriptions

15.2.1

A/D Data Registers A to D (ADDRA to ADDRD)

Bit 15 14
AD9 AD8
ADDRn
Initial value 0
Read/Write R R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
AN
0
AN
1
AN
2
AN
3
13 12 11 10
AD7 AD6 AD5 AD4
0 0 0 0 0
R R R R
A/D conversion data
10-bit data giving an
A/D conversion result
Group 1
AN
4
AN
5
AN
6
AN
7
9 8 7 6
AD3 AD2 AD1 AD0 —
0 0 0 0
R R R R R
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev. 3.00 Mar 21, 2006 page 525 of 814
Section 15 A/D Converter
5 4 3 2 1
— — — —
0 0 0 0 0
R R R R
Reserved bits
REJ09B0302-0300
0
—
0
R