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Section 21 Electrical Characteristics
• Basic bus cycle: three-state access with one wait state
Figure 21.6 shows the timing of the external three-state access cycle with one wait state
inserted.
φ
A
to A
,
23
0
CS
to CS
7
0
AS
RD
(read)
D
to D
15
0
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
Rev. 3.00 Mar 21, 2006 page 644 of 814
REJ09B0302-0300
T
1
t
CYC
t
t
CH
CL
t
CF
t
cyc
t
AD
t
t
ASD
ACC3
t
AS1
t
t
ASD
ACC3
t
AS1
t
ACC1
t
ASD
t
AS1
t
WDS1
t
WDD
Figure 21.4 Basic Bus Cycle: Two-State Access
T
2
t
CR
t
t
SD
AH
t
t
SD
AH
t
t
RDS
RDH
t
t
SD
AH
t
WSW1
t
WDH
t
PCH
t
PCH
t
PCH
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