Renesas F-ZTAT H8 Series Hardware Manual page 259

Figure 8.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
T
2
φ
DREQ
Address
bus
RD
HWR LWR
,
Figure 8.17 Timing of DMAC Activation by Low DREQ
CPU cycle
T T T T T
1 2 1 2 d
Minimum 4 states
DMAC cycle
T T T T T
1 2 1 2 1
Next sampling point
DREQ Level in Normal Mode
DREQ DREQ
Rev. 3.00 Mar 21, 2006 page 231 of 814
Section 8 DMA Controller
CPU cycle
T T T T
2 1 2
1
REJ09B0302-0300