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Section 6 Bus Controller
φ
Address bus
CS
n
AS
RD
Read
D
to D
15
8
access
D to D
7
0
HWR
LWR
Write
access
D
to D
15
8
D to D
7
0
Note: n = 7 to 0
Figure 6.7 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)
Rev. 3.00 Mar 21, 2006 page 126 of 814
REJ09B0302-0300
T
1
Odd external address in area n
High
(Byte Access to Odd Address)
Bus cycle
T
2
Invalid
Valid
Undetermined data
Valid
T
3
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