Table of Contents
Advertisement
20.4.3
Selection of Waiting Time for Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR and bits DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator: Set STS2 to STS0, DIV1, and DIV0 so that the waiting time (for the clock to
stabilize) is at least 7 ms. Table 20.3 indicates the waiting times that are selected by STS2 to
STS0, DIV1, and DIV0 settings at various system clock frequencies.
External Clock:
Set STS2 to STS0, DIV0, and DIV1 so that the waiting time is at least 100 µs.
Table 20.3 Clock Frequency and Waiting Time for Clock to Settle
DIV1 DIV0 STS2 STS1 STS0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
—
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
—
Waiting
Time
18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit
8192
0.46
0.51
states
16384
0.91
1.0
states
32768
1.8
2.0
states
65536
3.6
4.1
states
131072
7.3
8.2
states
1024
0.057
0.064
states
Illegal
setting
8192
0.91
1.02
states
16384
1.8
2.0
states
32768
3.6
4.1
states
65536
7.3
8.2
states
131072
14.6
16.4
states
1024
0.11
0.13
states
Illegal
setting
Section 20 Power-Down State
0.65
0.8
1.0
1.3
1.3
1.6
2.0
2.7
2.7
3.3
4.1
5.5
5.5
6.6
8.2
10.9
10.9
13.1
16.4
21.8
0.085
0.10
0.13
0.17
1.4
1.6
2.0
2.7
2.7
3.3
4.1
5.5
5.5
6.6
8.2
10.9
10.9
13.1
16.4
21.8
21.8
26.2
32.8
43.7
0.17
0.20
0.26
0.34
Rev. 3.00 Mar 21, 2006 page 625 of 814
2.0
4.1
8.2
ms
4.1
8.2
16.4
8.2
16.4
32.8
16.4
32.8
65.5
32.8
65.5
131.1
0.26
0.51
1.0
4.1
8.2
16.4
ms
8.2
16.4
32.8
16.4
32.8
65.5
32.8
65.5
131.1
65.5
131.1 262.1
0.51
1.0
2.0
REJ09B0302-0300
Advertisement
Table of Contents
