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Section 7 Refresh Controller
Example 4: Connection to Multiple 4-Mbit DRAM Chips (16-Mbyte Mode): Figure 7.13
shows an example of interconnections to two 2CAS 4-Mbit DRAM chips, and the corresponding
address map. Up to four DRAM chips can be connected to area 3 by decoding upper address bits
A
and A
.
19
20
Figure 7.14 shows a setup procedure to be followed by a program for this example. The DRAM in
this example has 9-bit row addresses and 9-bit column addresses. Both chips must be refreshed
simultaneously, so the RFSH pin must be used.
H8/3052BF
Figure 7.13 Interconnections and Address Map for Multiple 2CAS
Rev. 3.00 Mar 21, 2006 page 170 of 814
REJ09B0302-0300
A
19
A to A
9
1
CS
3
HWR
LWR
RD
RFSH
D
to D
15
0
a. Interconnections (example)
H'600000
No. 1
DRAM area
H'67FFFF
H'680000
No. 2
DRAM area
H'6FFFFF
H'700000
Not used
H'7FFFFF
b. Address map
(Example)
2 CAS 4-Mbit DRAM with 9-bit
row address, 9-bit column
address, and
A to A
8
RAS
UCAS
LCAS
WE
OE
I/O
to I/O
15
A to A
8
RAS
UCAS
LCAS
WE
OE
I/O
to I/O
15
Area 3 (16-Mbyte mode)
CAS 4-Mbit DRAM Chips
CAS
CAS
×
16-bit organization
0
No. 1
0
0
No. 2
0
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