Renesas F-ZTAT H8 Series Hardware Manual page 242

Section 8 DMA Controller
Table 8.8 Register Functions in Repeat Mode
Register
23
MAR
23 7
All 1s
7
ETCRH
7
ETCRL
Legend:
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer
count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from
ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID
bits in DTCR. Specifically, MAR is restored as follows:
MAR ← MAR – (–1)
ETCRH and ETCRL should be initially set to the same value.
In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,
if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No
CPU interrupt is requested.
Rev. 3.00 Mar 21, 2006 page 214 of 814
REJ09B0302-0300
Function
Activated by
SCI 0 Receive-
Data-Full
Interrupt
Destination
address
0
register
Source
0
address
IOAR
register
Transfer
counter
0
0
Hold transfer
count
DTID DTSZ
· 2
Other
Activation Initial Setting
Source Destination or
address source address
register
Destination Source or
address destination
register address
Transfer Number of
counter transfers
Hold transfer Number of
count transfers
· ETCRL
Operation
Incremented or
decremented at
each transfer
until H'0000,
then restored to
initial value
Held fixed
Decremented
once per
transfer until
H'0000 is
reached, then
reloaded from
ETCRL
Held fixed