Renesas F-ZTAT H8 Series Hardware Manual page 537

The following equation calculates the bit rate register (BRR) setting from the system clock
frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error.
φ
N =
1488 × 2
Table 14.6 BRR Settings for Typical Bit Rate (bits/s) (when n = 0)
7.1424 10.00
Bit/s N Error N Error
9600 0 0.00 1 30.00 1 25.00 1 8.99
Table 14.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface)
φ φ φ φ (MHz)
7.1424
10
10.7136
13
14.2848
16
18
20
25
The bit rate error is calculated from the following equation.
Error (%) =
× 10
6
– 1
× B
2n–1
10.7136 13.00
N Error N Error
Maximum Bit Rate (bits/s)
9600
13441
14400
17473
19200
21505
24194
26882
33602
φ
1488 × 2 × B × (N + 1)
2n–1
Section 14 Smart Card Interface
φ φ φ φ (MHz)
14.2848 16.00
N Error N Error N Error
1 0.00 1 12.01 2 15.99 2 6.66
N
0
0
0
0
0
0
0
0
0
× 10 – 1 × 100
6
Rev. 3.00 Mar 21, 2006 page 509 of 814
18.00 20.00 25.00
N Error N Error
3 12.49
n
0
0
0
0
0
0
0
0
0
REJ09B0302-0300