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Section 10 16-Bit Integrated Timer Unit (ITU)
10.6
Usage Notes
This section describes contention and other matters requiring special attention during ITU
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure
10.61.
φ
Address bus
Internal write signal
Counter clear signal
TCNT
Figure 10.61 Contention between TCNT Write and Clear
Rev. 3.00 Mar 21, 2006 page 382 of 814
REJ09B0302-0300
TCNT write cycle
T
T
1
2
TCNT address
N
3
T
3
H'0000
state of a
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