Block Diagram - Renesas F-ZTAT H8 Series Hardware Manual

Section 8 DMA Controller
8.1.2

Block Diagram

Figure 8.1 shows a DMAC block diagram.
Internal IMIA0
interrupts IMIA1
IMIA2
IMIA3
TXI0
RXI0
DREQ0
DREQ1
TEND0
TEND1
Interrupt DEND0A
signals DEND0B
DEND1A
DEND1B
Data buffer
Legend:
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Rev. 3.00 Mar 21, 2006 page 186 of 814
REJ09B0302-0300
Internal address bus
Channel
Control logic
DTCR0A
DTCR0B
DTCR1A
DTCR1B
Channel
Internal data bus
Figure 8.1 Block Diagram of DMAC
Arithmetic-logic unit
Channel
0A
0
Channel
0B
Channel
1A
1
Channel
1B
Address buffer
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B