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Section 8 DMA Controller
Figure 8.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
T
2
φ
DREQ
Address
bus
RD
HWR, LWR
Figure 8.16 Timing of DMAC Activation by Falling Edge of DREQ
Rev. 3.00 Mar 21, 2006 page 230 of 814
REJ09B0302-0300
CPU cycle
T
T
T
T
T
1
2
1
2
d
Minimum 4 states
DMAC cycle
T
T
T
T
T
1
2
1
2
1
Next sampling point
DREQ in Normal Mode
DREQ
DREQ
CPU
cycle
DMAC cycle
T
T
T
T
2
d
1
2
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