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Section 6 Bus Controller
Read
access
Write
access
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)
Rev. 3.00 Mar 21, 2006 page 130 of 814
REJ09B0302-0300
φ
Address bus
CS
n
AS
RD
D
to D
15
8
D to D
7
0
HWR
LWR
D
to D
15
8
D to D
7
0
(Word Access)
Bus cycle
T
T
1
2
External address in area n
Valid
Valid
Valid
Valid
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