Serial Mode Register (Smr) - Renesas F-ZTAT H8 Series Hardware Manual

14.2.3

Serial Mode Register (SMR)

Bit 7 of SMR has a different function in smart card interface mode. The related serial control
register (SCR) changes from bit 1 to bit 0.
Bit 7
GM
Initial value 0
Read/Write R/W
Bit 7—GSM Mode (GM): Set at 0 when using the regular smart card interface. In GSM mode,
set to 1. When transmission is complete, initially the TEND flag set timing appears followed by
clock output restriction mode. Clock output restriction mode comprises serial control register bit 1
and bit 0.
Bit 7: GM Description
0 Using the regular smart card interface mode
The TEND flag is set 12.5 etu after the beginning of the start bit
Clock output on/off control only
1 Using the GSM mode smart card interface mode
The TEND flag is set 11.0 etu after the beginning of the start bit
Clock output on/off and fixed-high/fixed-low control (set in SCR)
Bits 6 to 0: Operate in the same way as for the normal SCI.
For details, see section 13.2.5, Serial Mode Register (SMR).
6 5
CHR PR O/E
0 0
R/W R/W R/W
Section 14 Smart Card Interface
4 3 2
STOP MP
0
0 0
R/W R/W
Rev. 3.00 Mar 21, 2006 page 501 of 814
1 0
CKS1 CKS0
0 0
R/W R/W
(Initial value)
REJ09B0302-0300