Block Diagram - Renesas F-ZTAT H8 Series Hardware Manual

Hide thumbs Also See for F-ZTAT H8 Series:
Table of Contents

Advertisement

Section 14 Smart Card Interface
14.1.2

Block Diagram

Figure 14.1 shows a block diagram of the smart card interface.
RDR
RxD
RSR
0
TxD
0
SCK
0
Legend:
SCMR:
Smart card mode register
RSR:
Receive shift register
RDR:
Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR:
Serial mode register
SCR:
Serial control register
SSR:
Serial status register
BRR:
Bit rate register
Rev. 3.00 Mar 21, 2006 page 496 of 814
REJ09B0302-0300
Module data bus
TDR
TSR
Parity generate
Parity check
Figure 14.1 Smart Card Interface Block Diagram
SCMR
SSR
SCR
SMR
Transmit/receive
Baud rate
control
generator
Clock
BRR
φ
φ/4
φ/16
φ/64
TXI
RXI
ERI
Internal
data
bus

Advertisement

Table of Contents
loading

Table of Contents