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Section 6 Bus Controller
16-Bit, Two-State-Access Areas: Figures 6.9 to 6.11 show the timing of bus control signals for a
16-bit, two-state-access area. In these areas, the upper address bus (D
even addresses and the lower address bus (D
cannot be inserted.
φ
Address bus
CS
AS
RD
Read
D
access
D to D
HWR
LWR
Write
access
D
D to D
Note: n = 7 to 0
Figure 6.9 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
Rev. 3.00 Mar 21, 2006 page 128 of 814
REJ09B0302-0300
Even external address in area n
n
to D
15
8
7
0
High
to D
15
8
7
0
(Byte Access to Even Address)
to D
) is used to access odd addresses. Wait states
7
0
Bus cycle
T
1
Valid
Invalid
Valid
Undetermined data
to D
) is used to access
15
8
T
2
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