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9.2
Port 1
9.2.1
Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9.1. The pin
functions differ between the expanded modes with on-chip ROM disabled, expanded modes with
on-chip ROM enabled, and single-chip mode. In modes 1 to 4 (expanded modes with on-chip
ROM disabled), they are address bus output pins (A
In modes 5 and 6 (expanded modes with on-chip ROM enabled), settings in the port 1 data
direction register (P1DDR) can designate pins for address bus output (A
In mode 7 (single-chip mode), port 1 is a generic input/output port.
When DRAM is connected to area 3, A
cycles. For details see section 7, Refresh Controller.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington transistor pair.
Port 1 pins
Port 1
to A
7
Modes 1 to 4
P1 /A
A (output)
7
7
7
P1 /A
A (output)
6
6
6
P1 /A
A (output)
5
5
5
P1 /A
A (output)
4
4
4
P1 /A
A (output)
3
3
3
P1 /A
A (output)
2
2
2
P1 /A
A (output)
1
1
1
P1 /A
A (output)
0
0
0
Figure 9.1 Port 1 Pin Configuration
to A
).
7
0
output row and column addresses in read and write
0
Modes 5 and 6
P1 (input)/A (output)
7
7
P1 (input)/A (output)
6
6
P1 (input)/A (output)
5
5
P1 (input)/A (output)
4
4
P1 (input)/A (output)
3
3
P1 (input)/A (output)
2
2
P1 (input)/A (output)
1
1
P1 (input)/A (output)
0
0
Rev. 3.00 Mar 21, 2006 page 249 of 814
Section 9 I/O Ports
to A
) or generic input.
7
0
Mode 7
P1 (input/output)
7
P1 (input/output)
6
P1 (input/output)
5
P1 (input/output)
4
P1 (input/output)
3
P1 (input/output)
2
P1 (input/output)
1
P1 (input/output)
0
REJ09B0302-0300
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