Renesas F-ZTAT H8 Series Hardware Manual page 486

Section 13 Serial Communication Interface
The BRR setting is calculated as follows:
Asynchronous mode:
φ
N =
64 × 2
2n–1
Synchronous mode:
φ
N =
8 × 2
2n–1
B: Bit rate (bits/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clock frequency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
n
0
1
2
3
The bit rate error in asynchronous mode is calculated as follows.
Error (%) =
Rev. 3.00 Mar 21, 2006 page 458 of 814
REJ09B0302-0300
× 10
6
– 1
× B
× 10
6
– 1
× B
Clock Source
φ
φ/4
φ/16
φ/64
φ × 10
6
(N + 1) × B × 64 × 2
2n–1
SMR Settings
CKS1
0
0
1
1
– 1 × 100
CKS0
0
1
0
1