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Appendix B Internal I/O Register
IER—IRQ Enable Register
Bit
7
—
Initial value
0
Read/Write
R/(W)
ISR—IRQ Status Register
Bit
7
—
Initial value
0
Read/Write
—
IRQ to IRQ flags
5
Bits 5 to 0
IRQ5F to IRQ0F
Note:
Only 0 can be written, to clear the flag.
*
Rev. 3.00 Mar 21, 2006 page 774 of 814
REJ09B0302-0300
6
5
—
IRQ5E
0
0
R/(W)
R/(W)
6
5
—
IRQ5F
0
0
—
R/(W) *
0
Setting and Clearing Conditions
0
[Clearing conditions]
• Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
• IRQnSC = 0, IRQn input is high, and interrupt exception
handling is carried out.
• IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
1
[Setting conditions]
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and a falling edge is generated in the IRQn input.
4
3
IRQ4E
IRQ3E
0
0
R/(W)
R/(W)
IRQ to IRQ enable
5
0
0 IRQ to IRQ interrupts are disabled
5
0
1 IRQ to IRQ interrupts are enabled
5
0
4
3
IRQ4F
IRQ3F
IRQ2F
0
0
R/(W) *
R/(W) *
H'F5
Interrupt controller
2
1
IRQ2E
IRQ1E
0
0
R/(W)
R/(W)
H'F6
Interrupt controller
2
1
IRQ1F
IRQ0F
0
0
R/(W) *
R/(W) *
R/(W) *
0
IRQ0E
0
R/(W)
0
0
(n = 5 to 0)
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