Serial Status Register (Ssr) - Renesas F-ZTAT H8 Series Hardware Manual

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Bit 2—Smart Card Data Inverter (SINV): Inverts data logic levels. This function is used in
combination with bit 3 to communicate with inverse-convention cards. SINV does not affect the
logic level of the parity bit. For parity settings, see section 14.3.4, Register Settings.
Bit 2: SINV
Description
0
Unmodified TDR contents are transmitted
Received data is stored unmodified in RDR
1
Inverted TDR contents are transmitted
Received data is inverted before storage in RDR
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0: SMIF
Description
0
Smart card interface function is disabled
1
Smart card interface function is enabled
14.2.2

Serial Status Register (SSR)

The function of SSR bit 4 is modified in the smart card interface. This change also causes a
modification to the setting conditions for bit 2 (TEND).
Bit
7
TDRE
Initial value
1
Read/Write
R/(W)*
Note: * Only 0 can be written, to clear the flag.
6
5
RDRF
ORER
ERS
0
0
R/(W)*
R/(W)*
R/(W)*
Error signal status (ERS)
Status flag indicating that an
error signal has been received
Section 14 Smart Card Interface
4
3
2
PER
TEND
0
0
1
R/(W)*
R
Transmit end
Status flag indicating
end of transmission
Rev. 3.00 Mar 21, 2006 page 499 of 814
(Initial value)
(Initial value)
1
0
MPB
MPBT
0
0
R
R/W
REJ09B0302-0300

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