Renesas F-ZTAT H8 Series Hardware Manual page 401

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Figure 10.51 shows an example in which GRA is set to function as an input capture register

buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the

input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because

of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous

GRA value is simultaneously transferred to BRA. Figure 10.52 shows the transfer timing.

Figure 10.51 Register Buffering (Example 2: Buffering of Input Capture Register)

Section 10 16-Bit Integrated Timer Unit (ITU)

Input capture A

Counter cleared by

input capture B

Rev. 3.00 Mar 21, 2006 page 373 of 814

REJ09B0302-0300