Data Transfer Control Registers (Dtcr) - Renesas F-ZTAT H8 Series Hardware Manual

8.3.4

Data Transfer Control Registers (DTCR)

The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the
operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and
DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address
mode.
DTCRA
Bit 7
DTE
Initial value 0
Read/Write R/W
Data transfer enable
Enables or disables
data transfer
Data transfer size
Selects byte or
word size
DTCRA is initialized to H'00 by a reset and in standby mode.
6 5
DTSZ SAID SAIDE
0 0
R/W R/W R/W
Source address
increment/decrement
Source address increment/
decrement enable
These bits select whether
the source address register
(MARA) is incremented,
decremented, or held fixed
during the data transfer
4 3 2
DTIE DTS2A
0 0 0
R/W R/W
Data transfer
interrupt enable
Enables or disables the
CPU interrupt at the end
of the transfer
Data transfer select
2A and 1A
These bits must both be
set to 1
Rev. 3.00 Mar 21, 2006 page 201 of 814
Section 8 DMA Controller
1 0
DTS1A DTS0A
0 0
R/W R/W
Data transfer
select 0A
Selects block
transfer mode
REJ09B0302-0300