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Page 5 REVISION HISTORY M32R-FPU Software Manual Rev. Date Description Page Summary 1.00 – First edition issued Jan 08, 2003 1.01 Hexadecimal Instruction Code Table corrected (BTST instruction) Oct 31, 2003 APPENDICES-3 Appendix Figure 3.1.1 corrected APPENDICES-8 Incorrect) *The E1 stage of the FDIV instruction requires 13 cycles.
Page 6: Table Of Contents
2.1.3 Operation instructions ................ 2-4 2.1.4 Branch instructions ................2-6 2.1.5 EIT-related instructions ..............2-8 2.1.6 DSP function instructions ..............2-8 2.1.7 Floating-point Instructions ..............2-11 2.1.8 Bit Operation Instructions ..............2-11 2.2 Instruction format ....................2-12 M32R-FPU Software Manual (Rev.1.01)
Page 7 Appendix 6.1.1 Rounding Mode ............Appendix-23 Appendix 6.1.2 Exception occurring in Step 1 ........Appendix-23 Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU ... Appendix-28 Appendix 7 Precautions ....................Appendix-29 Appendix 7.1 Precautions to be taken when aligning data ......Appendix-29 INDEX M32R-FPU Software Manual (Rev.1.01)
Page 8 This page left blank intentionally. M32R-FPU Software Manual (Rev.1.01)
Page 9 CHAPTER 1 CPU PROGRAMMIING MODEL CPU Register General-purpose Registers Control Registers Accumulator Program Counter Data Format Addressing Mode...
Page 10: Chapter 1 Cpu Programming Model
1.1 CPU Register 1.1 CPU Register The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are a 32- bit configuration.
Page 11: Cpu Programming Model
• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. • The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW instruction or the CLRPSW instruction. Figure 1.3.1 Control Registers M32R-FPU Software Manual (Rev.1.01)
Page 12: Processor Status Word Register: Psw (Cr0)
Condition Bit from operations (instruction dependent) The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs.
Page 13: Condition Bit Register: Cbr (Cr1)
PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned (PC always returns to the word-aligned address). At reset release, the value of the BPC is undefined. M32R-FPU Software Manual (Rev.1.01)
Page 14: Floating-Point Status Register: Fpsr (Cr7)
Enable Bit 1: Execute EIT processing when a zero divide exception occurs 0: Mask EIT processing to be executed when an Overflow Exception overflow exception occurs Enable Bit 1: Execute EIT processing when an overflow exception occurs M32R-FPU Software Manual (Rev.1.01)
Page 15 Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs. Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write). M32R-FPU Software Manual (Rev.1.01)
Page 16: Floating-Point Exceptions (Fpe)
DN = 1: 0 is returned Note 1: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "1" M32R-FPU Software Manual (Rev.1.01)
Page 17 Note 2: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "1" Please note that the DIV0 EIT processing does not occur in the following conditions. Dividend Behavior An invalid operation exception occurs infinity No exception occur (with the result "infinity") M32R-FPU Software Manual (Rev.1.01)
Page 18 The destination register remains unchanged. Note: • A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs. 1-10 M32R-FPU Software Manual (Rev.1.01)
Page 19: Accumulator
The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R CPU instruction starts with even- numbered addresses, the LSB (bit 31) is always "0". At reset release, the value of the PC is "H’0000 0000." 1-11 M32R-FPU Software Manual (Rev.1.01)
Page 20: Data Format
1.6 Data Format 1.6 Data Format 1.6.1 Data Type The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16, and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2's complements.
Page 21: Data Format
1.6.2 Data Format (1) Data format in a register The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded into the register.
Page 22 Address +0 address +1 address +2 address +3 address 15 16 23 24 byte byte byte byte byte halfword half word halfword word word Figure 1.6.3 Data Format in Memory 1-14 M32R-FPU Software Manual (Rev.1.01)
Page 23: Addressing Mode
The contents of the register specify the memory address, then 4 is added to the register contents. (Can only be specified with LD instruction). • Add 2 to register contents [@R+] [M32R-FPU extended addressing mode] The contents of the register specify the memory address, then 2 is added to the register contents.
Page 24 CPU PROGRAMMING MODEL 1.7 Addressing Mode This page left blank intentionally. 1-16 M32R-FPU Software Manual (Rev.1.01)
Page 25: Chapter 2 Instruction Set
CHAPTER 2 INSTRUCTION SET 2.1 Instruction set overview 2.2 Instruction format...
Page 26: Load/Store Instructions
2.1 Instruction set overview 2.1 Instruction set overview The M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture. Memory is accessed by using the load/store instructions and other operations are executed by using register-to-register operation instructions.
Page 27 The contents of the register specify the memory address, then 4 is added to the register contents. (Can only be specified with LD instruction). • Add 2 to register contents [@R+] [M32R-FPU extended addressing mode] The contents of the register specify the memory address, then 2 is added to the register contents.
Page 28: Transfer Instructions
• arithmetic operation instructions ADD3 Add 3-operand ADDI Add immediate ADDV Add with overflow checking ADDV3 Add 3-operand with overflow checking ADDX Add with carry Negate Subtract SUBV Subtract with overflow checking SUBX Subtract with borrow M32R-FPU Software Manual (Rev.1.01)
Page 29 SLL3 Shift left logical 3-operand SLLI Shift left logical immediate Shift right arithmetic SRA3 Shift right arithmetic 3-operand SRAI Shift right arithmetic immediate Shift right logical SRL3 Shift right logical 3-operand SRLI Shift right logical immediate M32R-FPU Software Manual (Rev.1.01)
Page 30: Branch Instructions
Branch on not C-bit Branch on not equal to BNEZ Branch on not equal to zero Branch Jump and link Jump No operation Only a word-aligned (word boundary) address can be specified for the branch address. M32R-FPU Software Manual (Rev.1.01)
Page 31 C. 1 word (32 bits) address branch instruction H'00 instruction A instruction B H'04 instruction C instruction D H'08 instruction E H'0C instruction F H'10 instruction G instruction H Fig. 2.1.1 Branch addresses of branch instruction M32R-FPU Software Manual (Rev.1.01)
Page 32: Eit-Related Instructions
MVFACHI Move high-order word from accumulator MVFACLO Move low-order word from accumulator MVFACMI Move middle-order word from accumulator MVTACHI Move high-order word to accumulator MVTACLO Move low-order word to accumulator Round accumulator RACH Round accumulator halfword M32R-FPU Software Manual (Rev.1.01)
Page 33 Note: The location in the accumulator of the result and the appropriate sign extension are performed in the execution of the DSP function instruction. Refer to Chapter 3 for details. Fig. 2.1.2 DSP function instruction operation 1 (multiply, multiply and accumulate) M32R-FPU Software Manual (Rev.1.01)
Page 34 Fig. 2.1.3 DSP function instruction operation 2 (round off) MVFACMI instruction 15 16 31 32 47 48 Rsrc MVFACHI MVFACLO instruction instruction MVTACHI MVTACLO instruction instruction 31 32 Rdest Fig. 2.1.4 DSP function instruction operation 3 (transfer between accumulator and register) 2-10 M32R-FPU Software Manual (Rev.1.01)
Page 35: Floating-Point Instructions
Floating-point compare with exeption if unordered 2.1.8 Bit Operation Instructions These instructions determine the operation of the bit specified by the register or memory. BSET Bit set BCLR Bit clear BTST Bit test SETPSW Set PSW CLRPSW Clear PSW 2-11 M32R-FPU Software Manual (Rev.1.01)
Page 36: Instruction Format
Branch (Short Displacement) cond < 32-bit instruction > op c Compare and Branch op c cond Branch Floating-point 2-operand 0000 0000 =op(R Floating-point 3-operand 0000 1 op R Fig. 2.2.2 Instruction format of M32R CPU 2-12 M32R-FPU Software Manual (Rev.1.01)
Page 37 The current implementation allows only the NOP instruction as instruction B for parallel execution. The MSB of the NOP instruction used for word arraignment adjustment is changed to "1" automatically by a standard Mitsubishi assembler, then the M32R-FPU can execute this instruction without requiring any clock cycles.
Page 38 INSTRUCTION SET 2.2 Instruction format This page left blank intentionally. 2-14 M32R-FPU Software Manual (Rev.1.01)
Page 39: Conventions For Instruction Description
CHAPTER 3 INSTRUCTIONS 3.1 Conventions for instruction description 3.2 Instruction description...
Page 40: Conventions For Instruction Description
Indicates the operation performed by one instruction. Notation is in accordance with C language notation. Table 3.1.2 Operation expression (operator) operator meaning addition (binomial operator) subtraction (binomial operator) multiplication (binomial operator) division (binomial operator) remainder operation (binomial operator) increment (monomial operator) decrement (monomial operator) M32R-FPU Software Manual (Rev.1.01)
Page 41 –2,147,483,648 to +2,147,483,647 unsigned char 0 to 255 unsigned short 0 to 655,535 unsigned int 0 to 4,294,967,295 signed64bit signed 64-bit integer (with accumulator) Table 3.1.6 Data type (floating-point) expression floating-point format float single precision values format M32R-FPU Software Manual (Rev.1.01)
Page 42 Any immediate or displacement value is put in the imm or disp field, its maximum size being determined by the width of the field provided for the particular instruction. Refer to 2.2 Instruction format for detail. M32R-FPU Software Manual (Rev.1.01)
Page 43 INSTRUCTIONS 3.2 Instruction description 3.2 Instruction description This section lists M32R-FPU instructions in alphabetical order. Each page is laid out as shown below. arithmetic oper instruction name (instruction type and full name are in center) instruction mnemonic [Mnemonic] Add Rdest,Rsrc...
Page 44 [Mnemonic] Rdest,Rsrc [Function] Rdest = Rdest + Rsrc; [Description] ADD adds Rsrc to Rdest and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0000 dest 1010 ADD Rdest,Rsrc M32R-FPU Software Manual (Rev.1.01)
Page 45 ADD3 adds the 16-bit immediate value to Rsrc and puts the result in Rdest. The immediate value is sign-extended to 32 bits before the operation. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1000 dest 1010 imm16 ADD3 Rdest,Rsrc,#imm16 M32R-FPU Software Manual (Rev.1.01)
Page 46 ADDI adds the 8-bit immediate value to Rdest and puts the result in Rdest. The immediate value is sign-extended to 32 bits before the operation. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0100 dest imm8 ADDI Rdest,#imm8 M32R-FPU Software Manual (Rev.1.01)
Page 47 ADDV adds Rsrc to Rdest and puts the result in Rdest. The condition bit (C) is set when the addition results in overflow; otherwise it is cleared. [EIT occurrence] None [Encoding] 0000 dest 1000 ADDV Rdest,Rsrc M32R-FPU Software Manual (Rev.1.01)
Page 48 32 bits before it is added to Rsrc. The condition bit (C) is set when the addition results in overflow; otherwise it is cleared. [EIT occurrence] None [Encoding] 1000 dest 1000 imm16 ADDV3 Rdest,Rsrc,#imm16 3-10 M32R-FPU Software Manual (Rev.1.01)
Page 49 ADDX adds Rsrc and C to Rdest, and puts the result in Rdest. The condition bit (C) is set when the addition result cannot be represented by a 32-bit unsigned integer; otherwise it is cleared. [EIT occurrence] None [Encoding] 0000 dest 1001 ADDX Rdest,Rsrc 3-11 M32R-FPU Software Manual (Rev.1.01)
Page 50 [Description] AND computes the logical AND of the corresponding bits of Rdest and Rsrc and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] dest 0000 1100 AND Rdest,Rsrc 3-12 M32R-FPU Software Manual (Rev.1.01)
Page 51 AND3 computes the logical AND of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended to 32 bits, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1000 dest 1100 imm16 AND3 Rdest,Rsrc,#imm16 3-13 M32R-FPU Software Manual (Rev.1.01)
Page 52 There are two instruction formats; which allows software, such as an assembler, to decide on the better format. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] pcdisp8 0111 1100 pcdisp8 pcdisp24 1111 1100 pcdisp24 3-14 M32R-FPU Software Manual (Rev.1.01)
Page 53 CPU. Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to the type of MCU. [EIT occurrence] None [Encoding] 1010 bitpos 0111 disp16 BCLR #bitpos,@(disp16,Rsrc) 3-15 M32R-FPU Software Manual (Rev.1.01)
Page 54 ( Rsrc1 == Rsrc2 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BEQ causes a branch to the specified label when Rsrc1 is equal to Rsrc2. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 src1 0000 src2 pcdisp16 Rsrc1,Rsrc2,pcdisp16 3-16 M32R-FPU Software Manual (Rev.1.01)
Page 55 ( Rsrc == 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BEQZ causes a branch to the specified label when Rsrc is equal to zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 0000 1000 pcdisp16 BEQZ Rsrc,pcdisp16 3-17 M32R-FPU Software Manual (Rev.1.01)
Page 56 BGEZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is greater than or equal to zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 0000 1011 pcdisp16 BGEZ Rsrc,pcdisp16 3-18 M32R-FPU Software Manual (Rev.1.01)
Page 57 BGTZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is greater than zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 0000 1101 pcdisp16 BGTZ Rsrc,pcdisp16 3-19 M32R-FPU Software Manual (Rev.1.01)
Page 58 There are two instruction formats; this allows software, such as an assembler, to decide on the better format. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] pcdisp8 0111 1110 pcdisp8 pcdisp24 1111 1110 pcdisp24 3-20 M32R-FPU Software Manual (Rev.1.01)
Page 59 BLEZ causes a branch to the specified label when the contents of Rsrc treated as a signed 32- bit value, is less than or equal to zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 0000 1100 pcdisp16 BLEZ Rsrc,pcdisp16 3-21 M32R-FPU Software Manual (Rev.1.01)
Page 60 BLTZ causes a branch to the specified label when Rsrc treated as a signed 32-bit value is less than zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 0000 1010 pcdisp16 BLTZ Rsrc,pcdisp16 3-22 M32R-FPU Software Manual (Rev.1.01)
Page 61 There are two instruction formats; this allows software, such as an assembler, to decide on the better format. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] pcdisp8 0111 1101 pcdisp8 pcdisp24 1111 1101 pcdisp24 3-23 M32R-FPU Software Manual (Rev.1.01)
Page 62 ( Rsrc1 != Rsrc2 ) PC = ( PC & 0xfffffffc ) + ((( signed short ) pcdisp16) << 2); [Description] BNE causes a branch to the specified label when Rsrc1 is not equal to Rsrc2. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 src1 0001 src2 pcdisp16 Rsrc1,Rsrc2,pcdisp16 3-24 M32R-FPU Software Manual (Rev.1.01)
Page 63 ( Rsrc != 0 ) PC = ( PC & 0xfffffffc ) + ( ( ( signed short ) pcdisp16 ) << 2); [Description] BNEZ causes a branch to the specified label when Rsrc is not equal to zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1011 0000 1001 pcdisp16 BNEZ Rsrc,pcdisp16 3-25 M32R-FPU Software Manual (Rev.1.01)
Page 64 There are two instruction formats; this allows software, such as an assembler, to decide on the better format. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] pcdisp8 0111 1111 pcdisp8 pcdisp24 1111 1111 pcdisp24 3-26 M32R-FPU Software Manual (Rev.1.01)
Page 65 CPU. Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to the type of MCU. [EIT occurrence] None [Encoding] 1010 bitpos 0110 disp16 BSET #bitpos,@(disp16,Rsrc) 3-27 M32R-FPU Software Manual (Rev.1.01)
Page 66 Take out the bit specified as bitpos within the Rsrc lower eight bits and sets it in the condition bit (C). bitpos becomes 0 to 7, MSB becomes 0 and LSB becomes 7. [EIT occurrence] None [Encoding] BTST #bitpos,Rsrc 0000 bitpos 1111 3-28 M32R-FPU Software Manual (Rev.1.01)
Page 67 SM, IE, and C of PSW to the corresponding SM, IE, and C bits. When b7 (LSB) or #imm8 is 1, the condition bit (C) goes to 0. All other bits remain unchanged. [EIT occurrence] None [Encoding] imm8 0111 0010 CLRPSW #imm8 3-29 M32R-FPU Software Manual (Rev.1.01)
Page 68 C = ( ( signed ) Rsrc1 < ( signed ) Rsrc2 ) ? 1:0; [Description] The condition bit (C) is set to 1 when Rsrc1 is less than Rsrc2. The operands are treated as signed 32-bit values. [EIT occurrence] None [Encoding] 0000 src1 0100 src2 Rsrc1,Rsrc2 3-30 M32R-FPU Software Manual (Rev.1.01)
Page 69 The condition bit (C) is set when Rsrc is less than 16-bit immediate value. The operands are treated as signed 32-bit values. The immediate value is sign-extended to 32-bit before the opera- tion. [EIT occurrence] None [Encoding] 1000 0000 0100 imm16 CMPI Rsrc,#imm16 3-31 M32R-FPU Software Manual (Rev.1.01)
Page 70 C = ( ( unsigned ) Rsrc1 < ( unsigned ) Rsrc2 ) ? 1:0; [Description] The condition bit (C) is set when Rsrc1 is less than Rsrc2. The operands are treated as un- signed 32-bit values. [EIT occurrence] None [Encoding] 0000 src1 0101 src2 CMPU Rsrc1,Rsrc2 3-32 M32R-FPU Software Manual (Rev.1.01)
Page 71 The condition bit (C) is set when Rsrc is less than the 16-bit immediate value. The operands are treated as unsigned 32-bit values. The immediate value is sign-extended to 32-bit before the operation. [EIT occurrence] None [Encoding] 1000 0000 0101 imm16 CMPUI Rsrc,#imm16 3-33 M32R-FPU Software Manual (Rev.1.01)
Page 72 The operands are treated as signed 32-bit values and the result is rounded toward zero. The condition bit (C) is unchanged. When Rsrc is zero, Rdest is unchanged. [EIT occurrence] None [Encoding] 1001 dest 0000 0000 0000 0000 0000 Rdest,Rsrc 3-34 M32R-FPU Software Manual (Rev.1.01)
Page 73 The operands are treated as unsigned 32-bit values and the result is rounded toward zero. The condition bit (C) is unchanged. When Rsrc is zero, Rdest is unchanged. [EIT occurrence] None [Encoding] 1001 dest 0001 0000 0000 0000 0000 DIVU Rdest,Rsrc 3-35 M32R-FPU Software Manual (Rev.1.01)
Page 74 [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Overflow (OVF) • Underflow (UDF) • Inexact Exception (IXCT) [Encoding] 1101 src1 0000 src2 0000 dest 0000 0000 FADD Rdest,Rsrc1,Rsrc2 3-36 M32R-FPU Software Manual (Rev.1.01)
Page 75 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding toward any other direction. 3-37 M32R-FPU Software Manual (Rev.1.01)
Page 76 The DN bit of FPSR handles the conversion of denormalized numbers. The condition bit (C) remains unchanged. [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) [Encoding] 1101 src1 0000 src2 0000 dest 1100 0000 FCMP Rdest,Rsrc1,Rsrc2 3-38 M32R-FPU Software Manual (Rev.1.01)
Page 77 00000000 +Infinity Denormalized -0, - Number +Infinity 00000000 Rsrc1 +Infinity -Infinity 00000000 -Infinity comparison QNaN invalid SNaN IVLD IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN 3-39 M32R-FPU Software Manual (Rev.1.01)
Page 78 The DN bit of FPSR handles the conversion of denormalized numbers. The condition bit (C) remains unchanged. [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) [Encoding] 1101 src1 0000 src2 0000 dest 1101 0000 FCMPE Rdest,Rsrc1,Rsrc2 3-40 M32R-FPU Software Manual (Rev.1.01)
Page 79 +0, + Number 00000000 +Infinity Denormalized -0, - Number Rsrc1 00000000 +Infinity +Infinity 00000000 -Infinity -Infinity QNaN IVLD SNaN IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN 3-41 M32R-FPU Software Manual (Rev.1.01)
Page 80 • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Overflow (OVF) • Underflow (UDF) • Inexact Exception (IXCT) • Zero Divide Exception (DIV0) [Encoding] 1101 src1 0000 src2 0010 dest 0000 0000 FDIV Rdest,Rsrc1,Rsrc2 3-42 M32R-FPU Software Manual (Rev.1.01)
Page 81 Number +Infinity -Infinity +Infinity Rsrc1 Infinity IVLD -Infinity +Infinity -Infinity QNaN QNaN SNaN IVLD IVLD: Invalid Operation Exception UIPL: Unimplemented Exception DIV0: Zero Divide Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN 3-43 M32R-FPU Software Manual (Rev.1.01)
Page 82 [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Overflow (OVF) • Underflow (UDF) • Inexact Exception (IXCT) [Encoding] 1101 src1 0000 src2 0011 dest 0000 0000 FMADD Rdest,Rsrc1,Rsrc2 3-44 M32R-FPU Software Manual (Rev.1.01)
Page 83 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding toward any other direction. 3-45 M32R-FPU Software Manual (Rev.1.01)
Page 84 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding toward any other direction. 3-46 M32R-FPU Software Manual (Rev.1.01)
Page 85 [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Overflow (OVF) • Underflow (UDF) • Inexact Exception (IXCT) [Encoding] 1101 src1 0000 src2 0011 dest 0100 0000 FMSUB Rdest,Rsrc1,Rsrc2 3-47 M32R-FPU Software Manual (Rev.1.01)
Page 86 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding toward any other direction. 3-48 M32R-FPU Software Manual (Rev.1.01)
Page 87 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding toward any other direction. 3-49 M32R-FPU Software Manual (Rev.1.01)
Page 88 [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Overflow (OVF) • Underflow (UDF) • Inexact Exception (IXCT) [Encoding] 1101 src1 0000 src2 0001 dest 0000 0000 FMUL Rdest,Rsrc1,Rsrc2 3-50 M32R-FPU Software Manual (Rev.1.01)
Page 89 IVLD Denormalized -0, - Number Rsrc1 +Infinity +Infinity -Infinity Infinity IVLD +Infinity -Infinity -Infinity QNaN QNaN SNaN IVLD IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN 3-51 M32R-FPU Software Manual (Rev.1.01)
Page 90 [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Overflow (OVF) • Underflow (UDF) • Inexact Exception (IXCT) [Encoding] 1101 src1 0000 src2 0000 dest 0100 0000 FSUB Rdest,Rsrc1,Rsrc2 3-52 M32R-FPU Software Manual (Rev.1.01)
Page 91 IVLD: Invalid Operation Exception UIPL: Unimplemented Exception NaN: Not a Number SNaN: Signaling NaN QNaN: Quiet NaN Note: The rounding mode is “-0” when rounding toward “-Infinity”, and “+0” when rounding toward any other direction. 3-53 M32R-FPU Software Manual (Rev.1.01)
Page 92 The result is rounded toward 0 regardless of the value in the RM field of FPSR. The condition bit (C) remains unchanged. [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Inexact Exception (IXCT) [Encoding] 1101 0000 0000 0100 dest 1000 0000 FTOI Rdest,Rsrc 3-54 M32R-FPU Software Manual (Rev.1.01)
Page 93 Invalid Operation Exception Other EIT: SNaN Signed bit = 0:H’7FFF FFFF Signed bit = 1:H’8000 0000 Note 1: Inexact Exception occurs when rounding is performed. 2: Inexact Exception does not occur when Rsrc = H’CF00 0000. 3-55 M32R-FPU Software Manual (Rev.1.01)
Page 94 The result is rounded toward 0 regardless of the value in the RM field of FPSR. The condition bit (C) remains unchanged. [EIT occurrence] Floating-Point Exceptions (FPE) • Unimplemented Operation Exception (UIPL) • Invalid Operation Exception (IVLD) • Inexact Exception (IXCT) [Encoding] 1101 0000 0000 0100 dest 1100 0000 FTOS Rdest,Rsrc 3-56 M32R-FPU Software Manual (Rev.1.01)
Page 95 Note 1: Inexact Exception occurs when rounding is performed. 2: No Exceptions occur when Rsrc = H’C700 0000. When Rsrc = H’C700 0001 to H’C700 00FF, the Inexact Exception occurs and the Invalid Operation Exception does not occur. 3-57 M32R-FPU Software Manual (Rev.1.01)
Page 96 Rdest. The result is rounded according to the RM field of FPSR. The condition bit (C) remains unchanged. H’0000 0000 is handled as “+0” regardless of the Rounding Mode. [EIT occurrence] Floating-Point Exceptions (FPE) • Inexact Exception (IXCT) [Encoding] 1101 0000 0000 0100 dest 0000 0000 ITOF Rdest,Rsrc 3-58 M32R-FPU Software Manual (Rev.1.01)
Page 97 PC = Rsrc & 0xfffffffc; [Description] JL causes an unconditional jump to the address specified by Rsrc and puts the return address in R14. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 1110 1100 Rsrc 3-59 M32R-FPU Software Manual (Rev.1.01)
Page 98 [Mnemonic] Rsrc [Function] Jump PC = Rsrc & 0xfffffffc; [Description] JMP causes an unconditional jump to the address specified by Rsrc. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1100 0001 1111 Rsrc 3-60 M32R-FPU Software Manual (Rev.1.01)
Page 99 The displacement value is sign-extended to 32 bits before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] Address exception (AE) [Encoding] 1100 0010 dest Rdest,@Rsrc 0010 dest Rdest,@Rsrc+ 1110 1010 dest disp16 1100 Rdest,@(disp16,Rsrc) 3-61 M32R-FPU Software Manual (Rev.1.01)
Page 100 Rdest = imm24 & 0x00ffffff; [Description] LD24 loads the 24-bit immediate value into Rdest. The immediate value is zero-extended to 32 bits. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] imm24 1110 dest LD24 Rdest,#imm24 3-62 M32R-FPU Software Manual (Rev.1.01)
Page 101 16-bit displacement, and loads it into Rdest. The displacement value is sign-extended to 32 bits before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0010 dest 1000 Rdest,@Rsrc 1010 dest disp16 1000 Rdest,@(disp16,Rsrc) 3-63 M32R-FPU Software Manual (Rev.1.01)
Page 102 16-bit displacement, and loads it into Rdest. The displacement value is sign-extended to 32 bits before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] Address exception (AE) [Encoding] 0010 dest 1010 Rdest,@Rsrc 1010 dest disp16 1010 Rdest,@(disp16,Rsrc) 3-64 M32R-FPU Software Manual (Rev.1.01)
Page 103 (2) LDI loads the 16-bit immediate value into Rdest. The immediate value is sign-extended to 32 bits. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0110 dest imm8 Rdest,#imm8 1001 dest imm16 1111 0000 Rdest,#imm16 3-65 M32R-FPU Software Manual (Rev.1.01)
Page 104 16-bit displacement, and loads it into Rdest. The displacement value is sign-extended to 32 bits before address calculation. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0010 dest 1001 LDUB Rdest,@Rsrc 1010 dest disp16 1001 LDUB Rdest,@(disp16,Rsrc) 3-66 M32R-FPU Software Manual (Rev.1.01)
Page 105 The displacement value is sign-extended to 32 bits before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] Address exception (AE) [Encoding] 0010 dest 1011 LDUH Rdest,@Rsrc 1010 dest disp16 1011 LDUH Rdest,@(disp16,Rsrc) 3-67 M32R-FPU Software Manual (Rev.1.01)
Page 106 CPU. Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to the type of MCU. [EIT occurrence] Address exception (AE) [Encoding] 0010 dest 1101 LOCK Rdest,@Rsrc 3-68 M32R-FPU Software Manual (Rev.1.01)
Page 107 Value in accumulator before the execution of the MACHI instruction Value in accumulator after the Sign extension execution of the MACHI instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0100 src2 MACHI Rsrc1,Rsrc2 3-69 M32R-FPU Software Manual (Rev.1.01)
Page 108 Value in accumulator before the execution of the MACLO instruction Value in accumulator after the Sign extension execution of the MACLO instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0101 src2 MACLO Rsrc1,Rsrc2 3-70 M32R-FPU Software Manual (Rev.1.01)
Page 109 Value in accumulator before the execution of the MACWHI instruction Value in accumulator after the Sign extension execution of the MACWHI instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0110 src2 MACWHI Rsrc1,Rsrc2 3-71 M32R-FPU Software Manual (Rev.1.01)
Page 110 Value in accumulator before the execution of the MACWLO instruction Value in accumulator after the Sign extension execution of the MACWLO instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0111 src2 MACWLO Rsrc1,Rsrc2 3-72 M32R-FPU Software Manual (Rev.1.01)
Page 111 MUL multiplies Rdest by Rsrc and puts the result in Rdest. The operands are treated as signed values. The contents of the accumulator are destroyed by this instruction. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 dest 0110 Rdest,Rsrc 3-73 M32R-FPU Software Manual (Rev.1.01)
Page 112 16 bits Rsrc1 Rsrc2 high-order 16 bits Value in accumulator after the Sign extension execution of the MALHI instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0000 src2 MULHI Rsrc1,Rsrc2 3-74 M32R-FPU Software Manual (Rev.1.01)
Page 113 16 bits Rsrc1 Rsrc2 low-order 16 bits Value in accumulator after the Sign extension execution of the MULLO instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0001 src2 MULLO Rsrc1,Rsrc2 3-75 M32R-FPU Software Manual (Rev.1.01)
Page 114 32 bits Rsrc1 Rsrc2 high-order 16 bits Value in accumulator after the Sign extension execution of the MULWHI instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0010 src2 MULWHI Rsrc1,Rsrc2 3-76 M32R-FPU Software Manual (Rev.1.01)
Page 115 32 bits Rsrc1 low-order 16 bits Rsrc2 Value in accumulator after the Sign extension execution of the MULWLO instruction 15 16 31 32 47 48 [EIT occurrence] None [Encoding] 0011 src1 0011 src2 MULWLO Rsrc1,Rsrc2 3-77 M32R-FPU Software Manual (Rev.1.01)
Page 116 INSTRUCTIONS 3.2 Instruction description transfer instruction Move register [Mnemonic] Rdest,Rsrc [Function] Transfer Rdest = Rsrc; [Description] MV moves Rsrc to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 dest 1000 Rdest,Rsrc 3-78 M32R-FPU Software Manual (Rev.1.01)
Page 117 Rdest = ( int ) ( accumulator >> 32 ) ; [Description] MVFACHI moves the high-order 32 bits of the accumulator to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 dest 1111 0000 MVFACHI Rdest 3-79 M32R-FPU Software Manual (Rev.1.01)
Page 118 Transfer from accumulator to register Rdest = ( int ) accumulator [Description] MVFACLO moves the low-order 32 bits of the accumulator to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 dest 1111 0001 MVFACLO Rdest 3-80 M32R-FPU Software Manual (Rev.1.01)
Page 119 Rdest = ( int ) ( accumulator >> 16 ) ; [Description] MVFACMI moves bits16 through 47 of the accumulator to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 dest 1111 0010 MVFACMI Rdest 3-81 M32R-FPU Software Manual (Rev.1.01)
Page 120 [Mnemonic] MVFC Rdest,CRsrc [Function] Transfer from control register to register Rdest = CRsrc ; [Description] MVFC moves CRsrc to Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 dest 1001 MVFC Rdest,CRsrc 3-82 M32R-FPU Software Manual (Rev.1.01)
Page 121 [ 0 : 31 ] = Rsrc ; [Description] MVTACHI moves Rsrc to the high-order 32 bits of the accumulator. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 0111 0000 MVTACHI Rsrc 3-83 M32R-FPU Software Manual (Rev.1.01)
Page 122 [ 32 : 63 ] = Rsrc ; [Description] MVTACLO moves Rsrc to the low-order 32 bits of the accumulator. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 0111 0001 MVTACLO Rsrc 3-84 M32R-FPU Software Manual (Rev.1.01)
Page 123 CRdest = Rsrc ; [Description] MVTC moves Rsrc to CRdest. If PSW(CR0) is specified as CRdest, the condition bit (C) is changed; otherwise it is un- changed. [EIT occurrence] None [Encoding] 0001 dest 1010 MVTC Rsrc,CRdest 3-85 M32R-FPU Software Manual (Rev.1.01)
Page 124 Rdest = 0 – Rsrc ; [Description] NEG negates (changes the sign of) Rsrc treated as a signed 32-bit value, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0000 dest 0011 Rdest,Rsrc 3-86 M32R-FPU Software Manual (Rev.1.01)
Page 125 3.2 Instruction description branch instruction No operation [Mnemonic] [Function] No operation /* */ [Description] NOP performs no operation. The subsequent instruction then processed. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0111 0000 0000 0000 3-87 M32R-FPU Software Manual (Rev.1.01)
Page 126 Logical NOT Rdest = ~ Rsrc ; [Description] NOT inverts each of the bits of Rsrc and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0000 dest 1011 Rdest,Rsrc 3-88 M32R-FPU Software Manual (Rev.1.01)
Page 127 Rdest = Rdest | Rsrc ; [Description] OR computes the logical OR of the corresponding bits of Rdest and Rsrc, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0000 dest 1110 Rdest,Rsrc 3-89 M32R-FPU Software Manual (Rev.1.01)
Page 128 OR3 computes the logical OR of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended to 32 bits, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] imm16 1000 dest 1110 Rdest,Rsrc,#imm16 3-90 M32R-FPU Software Manual (Rev.1.01)
Page 129 = tmp & 0xffff ffff ffff 0000; } [Description] RAC rounds the contents in the accumulator to word size and stores the result in the accumu- lator. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 0000 1001 0000 3-91 M32R-FPU Software Manual (Rev.1.01)
Page 130 0000 0000 0000 0000 • • Bits 48 to 63 are cleared to zero. • • FFFF 8000 0000 8000 FFFF 8000 0000 7FFF negative • • value • • • • 8000 0000 0000 3-92 M32R-FPU Software Manual (Rev.1.01)
Page 131 = tmp & 0xffff ffff 0000 0000; } [Description] RACH rounds the contents in the accumulator to halfword size and stores the result in the accumulator. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 0000 1000 0000 RACH 3-93 M32R-FPU Software Manual (Rev.1.01)
Page 132 0000 0000 0000 0000 • • Bits 32 to 63 are cleared to zero. sign extension • • FFFF 8000 8000 0000 FFFF 8000 7FFF FFFF negative • • value • • • • 8000 0000 0000 3-94 M32R-FPU Software Manual (Rev.1.01)
Page 133 The quotient is rounded toward zero and the quotient takes the same sign as the dividend. The condition bit (C) is unchanged. When Rsrc is zero, Rdest is unchanged. [EIT occurrence] None [Encoding] 1001 dest 0010 0000 0000 0000 0000 Rdest,Rsrc 3-95 M32R-FPU Software Manual (Rev.1.01)
Page 134 REMU divides Rdest by Rsrc and puts the quotient in Rdest. The operands are treated as unsigned 32-bit values. The condition bit (C) is unchanged. When Rsrc is zero, Rdest is unchanged. [EIT occurrence] None [Encoding] 1001 dest 0011 0000 0000 0000 0000 REMU Rdest,Rsrc 3-96 M32R-FPU Software Manual (Rev.1.01)
Page 135 RTE restores the SM, IE and C bits of the PSW from the BSM, BIE and BC bits, and jumps to the address specified by BPC. At this time, because the BSM, BIE, and BC bits in the PSW register are undefined, the BPC is also undefined. [EIT occurrence] None [Encoding] 0001 0000 1101 0110 3-97 M32R-FPU Software Manual (Rev.1.01)
Page 136 SETH load the immediate value into the 16 most significant bits of Rdest. The 16 least significant bits become zero. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1101 dest 1100 0000 imm16 SETH Rdest,#imm16 3-98 M32R-FPU Software Manual (Rev.1.01)
Page 137 SM, IE, and C of PSW to the corresponding SM, IE, and C bits. When b7 (LSB) or #imm8 is 1, the condition bit (C) goes to 0. All other bits remain unchanged. [EIT occurrence] None [Encoding] imm8 0111 0001 SETPSW #imm8 [Note] Set the 8-bit immediate values of b2 to b6 to “0”. 3-99 M32R-FPU Software Manual (Rev.1.01)
Page 138 SLL left logical-shifts the contents of Rdest by the number specified by Rsrc, shifting zeroes into the least significant bits. Only the five least significant bits of Rsrc are used. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 dest 0100 Rdest,Rsrc 3-100 M32R-FPU Software Manual (Rev.1.01)
Page 139 Only the five least significant bits of the 16-bit immediate value are used. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1001 dest 1100 imm16 SLL3 Rdest,Rsrc,#imm16 3-101 M32R-FPU Software Manual (Rev.1.01)
Page 140 SLLI left logical-shifts the contents of Rdest by the number specified by the 5-bit immediate value, shifting zeroes into the least significant bits. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 dest imm5 SLLI Rdest,#imm5 3-102 M32R-FPU Software Manual (Rev.1.01)
Page 141 MSB of Rdest and puts the result in Rdest. Only the five least significant bits are used. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 dest 0010 Rdest,Rsrc 3-103 M32R-FPU Software Manual (Rev.1.01)
Page 142 Rsrc and puts the result in Rdest. Only the five least significant bits are used. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1001 dest 1010 imm16 SRA3 Rdest,Rsrc,#imm16 3-104 M32R-FPU Software Manual (Rev.1.01)
Page 143 SRAI right arithmetic-shifts the contents of Rdest by the number specified by the 5-bit immedi- ate value, replicates the sign bit in MSB of Rdest and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 dest imm5 SRAI Rdest,#imm5 3-105 M32R-FPU Software Manual (Rev.1.01)
Page 144 Rdest. Only the five least significant bits of Rsrc are used. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0001 dest 0000 Rdest,Rsrc 3-106 M32R-FPU Software Manual (Rev.1.01)
Page 145 Only the five least significant bits of the immediate value are valid. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 1001 dest 1000 imm16 SRL3 Rdest,Rsrc,#imm16 3-107 M32R-FPU Software Manual (Rev.1.01)
Page 146 SRLI right arithmetic-shifts Rdest by the number specified by the 5-bit immediate value, shift- ing zeroes into the most significant bits. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0101 dest imm5 SRLI Rdest,#imm5 3-108 M32R-FPU Software Manual (Rev.1.01)
Page 147 (4) ST stores Rsrc1 in the memory at the address specified by Rsrc combined with the 16-bit displacement. The displacement value is sign-extended before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] Address exception (AE) 3-109 M32R-FPU Software Manual (Rev.1.01)
Page 148 INSTRUCTIONS 3.2 Instruction description load/store instruction Store [Encoding] 0010 src1 Rsrc1,@Rsrc2 0100 src2 0010 src1 Rsrc1,@+Rsrc2 0110 src2 0010 src1 Rsrc1,@-Rsrc2 0111 src2 1010 src1 disp16 0100 src2 Rsrc1,@(disp16,Rsrc2) 3-110 M32R-FPU Software Manual (Rev.1.01)
Page 149 16-bit displacement. The displacement value is sign-extended to 32 bits before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] Rsrc1,@Rsrc2 0010 src1 0000 src2 1010 src1 disp16 0000 src2 Rsrc1,@(disp16,Rsrc2) 3-111 M32R-FPU Software Manual (Rev.1.01)
Page 150 32 bits before the address calculation. The condition bit (C) is unchanged. [EIT occurrence] Address exception (AE) [Encoding] 0010 src1 Rsrc1,@Rsrc2 0010 src2 0010 src1 Rsrc1,@Rsrc2+ 0011 src2 1010 src1 disp16 0010 src2 Rsrc1,@(disp16,Rsrc2) 3-112 M32R-FPU Software Manual (Rev.1.01)
Page 151 [Mnemonic] Rdest,Rsrc [Function] Subtract Rdest = Rdest - Rsrc; [Description] SUB subtracts Rsrc from Rdest and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] Rdest,Rsrc 0000 dest 0010 3-113 M32R-FPU Software Manual (Rev.1.01)
Page 152 SUBV subtracts Rsrc from Rdest and puts the result in Rdest. The condition bit (C) is set when the subtraction results in overflow; otherwise, it is cleared. [EIT occurrence] None [Encoding] SUBV Rdest,Rsrc 0000 dest 0000 3-114 M32R-FPU Software Manual (Rev.1.01)
Page 153 SUBX subtracts Rsrc and C from Rdest and puts the result in Rdest. The condition bit (C) is set when the subtraction result cannot be represented by a 32-bit unsigned integer; otherwise it is cleared. [EIT occurrence] None [Encoding] SUBX Rdest,Rsrc 0000 dest 0001 3-115 M32R-FPU Software Manual (Rev.1.01)
Page 154 ); [Description] TRAP generates a trap with the trap number specified by the 4-bit immediate value. IE and C bits are cleared to "0". [EIT occurrence] Trap (TRAP) [Encoding] 0001 0000 1111 imm4 TRAP #imm4; 3-116 M32R-FPU Software Manual (Rev.1.01)
Page 155 CPU. Refer to the Users Manual for non-CPU bus right requests, as the handling differs according to the type of M [EIT occurrence] Address exception (AE) [Encoding] 0010 src1 0101 src2 UNLOCK Rsrc1,@Rsrc2 3-117 M32R-FPU Software Manual (Rev.1.01)
Page 156 The condition bit (C) remains unchanged. H’0000 0000 is treated as “+0” regardless of the Rounding Mode. [EIT occurrence] Floating-Point Exceptions (FPE) • Inexact Exception (IXCT) [Encoding] 1101 0000 0000 0100 dest 0100 0000 UTOF Rdest,Rsrc 3-118 M32R-FPU Software Manual (Rev.1.01)
Page 157 Rdest = ( unsigned ) Rdest ^ ( unsigned ) Rsrc; [Description] XOR computes the logical XOR of the corresponding bits of Rdest and Rsrc, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] 0000 dest 1101 Rdest,Rsrc 3-119 M32R-FPU Software Manual (Rev.1.01)
Page 158 XOR3 computes the logical XOR of the corresponding bits of Rsrc and the 16-bit immediate value, which is zero-extended to 32 bits, and puts the result in Rdest. The condition bit (C) is unchanged. [EIT occurrence] None [Encoding] imm16 1000 dest 1101 XOR3 Rdest,Rsrc,#imm16 3-120 M32R-FPU Software Manual (Rev.1.01)
Page 159: Appendix 1 Hexadecimal Instraction Code
APPENDICES APPENDIX 1 Hexadecimal Instraction Code APPENDIX 2 Instruction List APPENDIX 3 Pipeline Processing APPENDIX 4 Instruction Execution Time APPENDIX 5 IEEE754 Specification Overview APPENDIX 6 M32R-FPU Specification Supplemental Explanation...
Page 160 Appendix 1 Hexadecimal Instraction Code Appendix1 Hexadecimal Instraction Code The bit pattern of each instruction and correspondence of mnemonic are shown below. The instructions enclosed in the bold lines are M32R-FPU extended instructions. Appendix Table 1.1.1 Instruction Code Table 0000...
Page 161 Note. In addition to b0-b3, b8-b11, instructions shown the above 2 in the table are decided by the following bit patterns. As for details of bit patterns of each instruction, refer to "3.2 Instruction description." 1: b4-b7, 2: b12-b15 APPENDICES-3 M32R-FPU Software Manual (Rev.1.01)
Page 162 APPENDIX 2 APPENDICES Appendix 2 Instruction List Appendix 2 Instruction List The M32R-FPU instruction list is shown below (in alphabetical order). mnemonic function condition bit (C) – Rdest,Rsrc Rdest = Rdest + Rsrc – ADD3 Rdest,Rsrc,#imm16 Rdest = Rsrc + (sh)imm16 –...
Page 163: Appendix 2 Instruction List
Rdest = accumulator – MVFACMI Rdest Rdest = accumulator >> 16 – MVFC Rdest,CRsrc Rdest = CRsrc – MVTACHI Rsrc accumulator[0:31] = Rsrc – MVTACLO Rsrc accumulator[32:63] = Rsrc MVTC Rsrc,CRdest CRdest = Rsrc change APPENDICES-5 M32R-FPU Software Manual (Rev.1.01)
Page 164 Call trap-handler number-n – UNLOCK Rsrc1,@Rsrc2 if(LOCK) { *(s *)Rsrc2 = Rsrc1; } LOCK=0 – UTOF Rdest,Rsrc Rdest = (float)(unsigned int) Rsrc; – Rdest,Rsrc Rdest = Rdest ^ Rsrc – XOR3 Rdest,Rsrc,#imm16 Rdest = Rsrc ^ (uh)imm16 APPENDICES-6 M32R-FPU Software Manual (Rev.1.01)
Page 165 /* 16 bit signed integer (halfword)*/ typedef unsigned short uh; /* 16 bit unsigned integer (halfword)*/ typedef signed char sb; /* 8 bit signed integer (byte)*/ typedef unsigned char ub; /* 8 bit unsigned integer (byte)*/ APPENDICES-7 M32R-FPU Software Manual (Rev.1.01)
Page 166: Appendix 3.1 Instructions And Pipeline Processing
The following is an example of a bypass process: ¥ E stage continuing to WB stage E, E1, EM stages ¥ MEM2 stage continuing to WB stage E, E1, EM, EA stages Appendix Figure 3.1.1 Instructions and Pipeline Process APPENDICES-8 M32R-FPU Software Manual (Rev.1.01)
Page 167 Operand accesses (OA) are processed in the MEM stage. This stage is used only when the load/store instruction is executed. WB stage (write back stage) The operation results and fetched data are written to the registers in the WB stage. APPENDICES-9 M32R-FPU Software Manual (Rev.1.01)
Page 168: Appendix 3.2 Pipeline Basic Operation
LD R0,@R2 MEM1 MEM1 MEM2 LDI R1,#1 ADD R1,R3 OR R1,R4 * A multi-cycle instruction, such as multiply or divide, executes multiple cycles in the E stage. Appendix Figure 3.2.1 Pipeline Flow with no Stall (1) APPENDICES-10 M32R-FPU Software Manual (Rev.1.01)
Page 169 * The FDIV instruction takes 14 cycles in E1 stage. <Case 5> Four FMADD or FMSUB instructions continue consecutively with no register dependency FMADD R0,R5,R6 FMADD R1,R6,R7 FMADD R2,R7,R8 FMADD R3,R80,R9 Appendix Figure 3.2.2 Pipeline Flow with no Stall (2) APPENDICES-11 M32R-FPU Software Manual (Rev.1.01)
Page 170 LD R1,@R2 MEM1 MEM1 MEM1 MEM2 •••• LD R3,@R4 stall stall MEM1 MEM2 •••• ADD R5,R6 stall stall •••• ADD R7,R8 stall stall •••• stall: a pipeline stall Appendix Figure 3.2.3 Pipeline Flow with Stalls (1) APPENDICES-12 M32R-FPU Software Manual (Rev.1.01)
Page 171 Bypass process ADD R4,R5 ADD R3, stall ,@R2 MEM1 MEM2 Bypass process ADD R4,R5 ADD R6,R7 ADD R3, ,@R2 MEM1 MEM2 Bypass process ADD R4,R5 FMADD ,R6,R7 Appendix Figure 3.2.4 Pipeline Flow with Stalls (2) APPENDICES-13 M32R-FPU Software Manual (Rev.1.01)
Page 172 <Case 7> The operation result of the FPU instruction is used by the subsequent instruction FADD ,R1,R2 FADD R3, stall stall FMADD ,R1,R2 FMADD ,R3,R4 stall stall FMADD ,R1,R2 FMADD R3, stall stall stall Appendix Figure 3.2.5 Pipeline Flow with Stalls (3) APPENDICES-14 M32R-FPU Software Manual (Rev.1.01)
Page 173 FMADD R7,R8,R9 <Case 11> The FMADD/FMSUB instructions run consecutively with the integer instruction (with register dependency) Bypass process FMADD stall stall stall stall stall stall FMADD ,R8,R9 Appendix Figure 3.2.6 Pipeline Flow with Stalls (4) APPENDICES-15 M32R-FPU Software Manual (Rev.1.01)
Page 174 <Case 13> The FPU and FMADD/FMSUB instructions run consecutively (with register dependency) FADD ,R1,R10 FMADD stall stall stall FADD ,R11 stall stall stall stall stall stall stall stall stall stall FMADD ,R8,R9 Appendix Figure 3.2.7 Pipeline Flow with Stalls (5) APPENDICES-16 M32R-FPU Software Manual (Rev.1.01)
Page 175: Appendix 4 Instruction Execution Time
FMADD, FMSUB instructions R (note 1) 1 FDIV instruction R (note 1) 1 other FPU instructions R (note 1) 1 Note 1: R, W: Refer to the user's manual prepared for each product. APPENDICES-17 M32R-FPU Software Manual (Rev.1.01)
Page 176: Appendix 5 Ieee754 Specification Overview
APPENDICES Appendix 5 IEEE754 Specification Overview Appendix 5 IEEE754 Specification Overview The following is a basic overview of the IEEE754 specification. M32R-FPU fulfills the IEEE754 requirements through a combination of software and hardware features. Appendix 5.1 Floating Point Formats The following describes the floating-point formats.
Page 177 QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware. APPENDICES-19 M32R-FPU Software Manual (Rev.1.01)
Page 178: Appendix 5.2 Rounding
–MAX Nearest +Infinity – –Infinity Note : • When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "0" • When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "1" APPENDICES-20 M32R-FPU Software Manual (Rev.1.01)
Page 179 (EXOR) of signs of divider and dividend.) Please note that the DIV0 EIT operation does not occur in the following factors. Dividend Operation Invalid Operation Exception occurs Infinity No Exception occurs (result is “Infinity”) APPENDICES-21 M32R-FPU Software Manual (Rev.1.01)
Page 180 The value resulting from calculations of infinite and unbounded exponent and mantissa bits. In actual implementation, the number of exponent and mantissa bits is finite and the intermediate result is rounded so that the final operation result can be determined. APPENDICES-22 M32R-FPU Software Manual (Rev.1.01)
Page 181: Appendix 6 M32R-Fpu Specification Supplemental Explanation
APPENDIX 6 APPENDICES Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs. two instructions (FMUL and FADD) The following is an explanation of the differences between an operation using just one instruction (FMADD or FMSUB) and an operation using 2 instructions (FMUL and FADD).
Page 182 APPENDIX 6 APPENDICES Appendix 6 M32R-FPU Specification Supplemental Explanation (1) Overflow occurs in Step 1 <When EO = 0, EX = 0: OVF and IXCT occur> Type of R0 Condition FMUL + FADD Operation FMADD Operation Normalized – R0 = OVF immediate...
Page 183 APPENDIX 6 APPENDICES Appendix 6 M32R-FPU Specification Supplemental Explanation (2) When underflow occurs in Step 1 <When EU = 0, DN = 1: UDF occurs> Type of R0 Condition FMUL + FADD Operation FMADD Operation Normalized – R0 = R0 + 0...
Page 184 APPENDIX 6 APPENDICES Appendix 6 M32R-FPU Specification Supplemental Explanation (3) When Invalid Operation Exception occurs in Step 1 If at least one of [R1, R2] is an SNaN <When EV = 0: IVLD occurs> Type of R0 Condition FMUL + FADD Operation...
Page 185 APPENDIX 6 APPENDICES Appendix 6 M32R-FPU Specification Supplemental Explanation (4) When Inexact Operation Exception occurs in Step 1 If an Inexact Operation occurs due to rounding: <When EX = 0: IXCT occurs> Type of R0 Condition FMUL + FADD Operation...
Page 186: Appendix 6.2 Rules Concerning Generation Of Qnan In M32R-Fpu
Appendix 6 M32R-FPU Specification Supplemental Explanation Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU T h e f o l l o w i n g a r e r u l e s c o n c e r n i n g g e n e r a t i n g a Q N a N a s a n o p e r a t i o n r e s u l t .
Page 187: Appendix 7 Precautions
In consideration of the upward compatibility of software when programming, if the high- order halfword has a 16-bit instruction, make sure that the following data area is aligned or allocated from an address that has an adjusted word alignment. 1 word 16-bit instruction data data APPENDICES-29 M32R-FPU Software Manual (Rev.1.01)
Page 188 APPENDIX 7 APPENDICES Appendix 7 Precautions This page left blank intentionally. APPENDICES-30 M32R-FPU Software Manual (Rev.1.01)
Page 189 INDEX...
Page 190 MULLO 3-75 BEQZ 3-17 MULWHI 3-76 BGEZ 3-18 MULWLO 3-77 BGTZ 3-19 MVFACHI 3-79 BL 3-20 MVFACLO 3-80 BLEZ 3-21 MVFACMI 3-81 BLTZ 3-22 MVTACHI 3-83 BNC 3-23 MVTACLO 3-84 BNE 3-24 RAC 3-91 RACH 3-93 INDEX-2 M32R-FPU Software Manual (Rev.1.01)
Page 191 1-15, 3-2 Instruction Execution Time APPENDICES-17 Instruction format 2-12 Instruction List APPENDICES-4 Instruction set overview 2-2 PC relative(pcdisp) 1-14, 3-2 Interrupt Stack Pointer(SPI) 1-2, 1-3, 1-5 Processor Status Register(PSW) 1-3, 1-4 Program Counter(PC) 1-11 INDEX-3 M32R-FPU Software Manual (Rev.1.01)
Page 192 SRA3 3-104 SRAI 3-105 SRL 3-106 SRL3 3-107 SRLI 3-108 Stack pointer 1-2, 1-5 Transfer instructions 2-4 LD24 3-62 LDI 3-65 MV 3-78 MVFC 3-82 MVTC 3-85 SETH 3-98 User Stack Pointer(SPU) 1-2, 1-3, 1-5 INDEX-4 M32R-FPU Software Manual (Rev.1.01)
Page 193 RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER SOFTWARE MANUAL M32R-FPU Publication Data : Rev.1.00 Jan 08, 2003 Rev.1.01 Oct 31, 2003 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 194 M32R-FPU Software Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0112-0101Z...

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