10
Count clock
Enable bit
H'FFFF
Counter
H'0000
Reload 0 register
Reload 1 register
F/F output
Interrupt request
due to underflow
Note: • This diagram does not show detailed timing information.
Figure 10.8.9 Typical Operation in PWM Output Mode
Enabled
(by writing to the enable bit
or by external input)
Count down from the
reload 0 register
set value
Undefined
H'C000
value
H'A000
H'(A000-1)
H'A000
H'C000
Data inverted
by enable
One count clock equivalent delay
10-180
MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
Underflow
Underflow
(first time)
(second time)
Count down from the
reload 1 register
set value
H'(C000-1)
H'A000
Data inverted
Data inverted
by underflow
by underflow
One count clock equivalent delay
PWM output period
One count clock equivalent delay
Count down from the
reload 0 register
set value
H'(A000-1)
32180 Group User's Manual (Rev.1.0)