Outline Of Tml Operation; Tml Related Register Map - Renesas M32R/ECU Series User Manual

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10.6.2 Outline of TML Operation

In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is
a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at
that point in time is stored in each 32-bit measure register.
When the reset input signal is deasserted, the counter starts operating with a BCLK/2 clock, and cannot be
stopped once it has started. The counter is idle only when the microcomputer remains reset.
A TIN interrupt request can be generated by external measure signal input. However, no TML counter overflow
interrupts are available.

10.6.3 TML Related Register Map

Shown below is a TML related register map.
TML Related Register Map
Address
b0
H'0080 03E0
H'0080 03E2
|
H'0080 03EA
|
H'0080 03F0
H'0080 03F2
H'0080 03F4
H'0080 03F6
H'0080 03F8
H'0080 03FA
H'0080 03FC
H'0080 03FE
|
H'0080 0FE0
H'0080 0FE2
|
H'0080 0FEA
|
H'0080 0FF0
H'0080 0FF2
H'0080 0FF4
H'0080 0FF6
H'0080 0FF8
H'0080 0FFA
H'0080 0FFC
H'0080 0FFE
+0 address
(Use inhibited area)
(Use inhibited area)
TML0 Measure 3 Register
TML0 Measure 2 Register
TML0 Measure 1 Register
TML0 Measure 0 Register
(Use inhibited area)
(Use inhibited area)
(Use inhibited area)
TML1 Measure 3 Register
TML1 Measure 2 Register
TML1 Measure 1 Register
TML1 Measure 0 Register
MULTIJUNCTION TIMERS
10.6 TML (Input-Related 32-Bit Timer)
+1 address
b7 b8
TML0 Counter
(TML0CT)
TML0 Control Register
(TML0MR3)
(TML0MR2)
(TML0MR1)
(TML0MR0)
TML1 Counter
(TML1CT)
TML1 Control Register
(TML1MR3)
(TML1MR2)
(TML1MR1)
(TML1MR0)
10-133
b15
(Upper)
(Lower)
(TML0CR)
(Upper)
(Lower)
(Upper)
(Lower)
(Upper)
(Lower)
(Upper)
(Lower)
(Upper)
(Lower)
(TML1CR)
(Upper)
(Lower)
(Upper)
(Lower)
(Upper)
(Lower)
(Upper)
(Lower)
32180 Group User's Manual (Rev.1.0)
See pages
10-135
10-134
10-135
10-135
10-135
10-135
10-135
10-134
10-135
10-135
10-135
10-135