Renesas M32R/ECU Series User Manual page 233

9
Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1
REQSL1 DMA Transfer Request Source
0 0 Software start
0 1 MJT (output event bus 0)
1 0 MJT (TIN13 input signal)
1 1 Extended DMA1 transfer request
source selected
REQESEL1 DMA Transfer Request Source
0000 One DMA0 transfer completed
0001 MJT (TIN3 input signal)
0010 MJT (TID1_udf/ovf)
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2
REQSL2 DMA Transfer Request Source
0 0 Software start
0 1 MJT (output event bus 1)
1 0 MJT (TIN18 input signal)
1 1 Extended DMA2 transfer request
source selected
REQESEL2 DMA Transfer Request Source
0000 One DMA0 transfer completed
0001 MJT(TID2_udf/ovf)
0010 CAN(CAN0_S1/S14)
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
9.3 Functional Description of the DMAC
DMA Transfer Request Generation Timing
When any data is written to the DMA1 Software Request Generation Register
When MJT output event bus 0 signal is generated
When MJT TIN13 input signal is generated
The source selected by the DMA1 Channel Control Register 1 (DM1CNT1)
REQESEL1 bits (see below)
DMA Transfer Request Generation Timing
When one DMA0 transfer is completed (cascade mode)
When MJT TIN3 input signal is generated
When MJT TID1 underflow/overflow occurs
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
–
DMA Transfer Request Generation Timing
When any data is written to the DMA2 Software Request Generation Register
When MJT output event bus 1 signal is generated
When MJT TIN18 input signal is generated
The source selected by the DMA2 Channel Control Register 1 (DM2CNT1)
REQESEL2 bits (see below)
DMA Transfer Request Generation Timing
When one DMA0 transfer is completed (cascade mode)
When MJT TID2 underflow/overflow occurs
When CAN0 slot 1 transmission failed or slot 14 transmission reception finished
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
–
9-28
32180 Group User's Manual (Rev.1.0)
DMAC