Outline Of Each Mode Of Tou - Renesas M32R/ECU Series User Manual

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10.8.2 Outline of Each Mode of TOU

Each mode of TOU is outlined below. Modes on each TOU channel can be selected from the following, only one
at a time.
(1) PWM output mode (without correction function)
In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
During PWM output mode, the timer operates as a 16-bit timer.
When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is
loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first
time the counter underflows, it is loaded with the reload 1 register value and continues counting. Thereafter,
the counter is loaded with the reload 0 and reload 1 register values alternately each time an underflow
occurs.
The F/F output waveform in PWM output mode is inverted when the counter starts counting and each time it
underflows. The timer stops at the same time count is disabled by writing to the enable bit (and not in
synchronism with PWM output period). An interrupt request and DMA transfer request can be generated
when the counter underflows every other time (second time, fourth time and so on) after being enabled.
(2) Single-shot PWM output mode (without correction function)
In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given
duty cycle only once. During PWM output mode, the timer operates as a 16-bit timer.
When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is
loaded with the reload 0 register value and starts counting down synchronously with the count clock. The first
time the counter underflows, it is loaded with the reload 1 register value and continues counting. The counter
stops when it underflows next time. The (reload 0 register set value + 1) and (reload 1 register set value + 1)
respectively are effective as count values.
The timer can be stopped in software, in which case it stops at the same time count is disabled by writing to
the enable bit (and not in synchronism with PWM output period).
The F/F output waveform in single-shot PWM output mode is inverted (F/F output level changes from low to
high or vice versa) each time the counter underflows. (Unlike in PWM output mode, the F/F output is not
inverted when the counter is enabled.)
An interrupt request and DMA transfer request can be generated when the counter underflows second time
after being enabled.
(3) Delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1)
after a finite time equal to (counter set value + 1) only once and then stops.
When the timer is enabled after setting the counter and reload register, it starts counting down from the
counter's set value synchronously with the count clock. The first time the counter underflows, it is loaded with
the reload register value and continues counting down. The counter stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted when the counter underflows first
time and next, generating a single-shot pulse waveform in width of (reload register set value + 1) after a finite
time equal to (first set value of counter + 1) only once.
An interrupt request and DMA transfer request can be generated when the counter underflows first time and
next.
MULTIJUNCTION TIMERS
10.8 TOU (Output-Related 24-Bit Timer)
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32180 Group User's Manual (Rev.1.0)