Page 1 Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.
Page 2 Mitsubishi 32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series 32180 32180 User's Manual http://www.infomicom.maec.co.jp/ The latest version of this manual is published at the Mitsubishi microcomputer home page shown above. Please make sure you are using the latest version of the manual.
Page 3 Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor prod- • ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appro- priate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap.
Page 4: Revision History
32180 Group User’s Manual Revision History Contents of Revision Rev. Date of Issue Page Changes Made – Jan. 24, 2003 First edition issued (1/1)
Page 5: Before Use
Before Use • Guide to Understanding the Register Table (1) Bit number: Indicates a register’s bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise.
Page 6: Table Of Contents
Table of contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32180 Group --------------------------------------------------------------------------------------------- 1-2 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) --------------------------------------------- 1-2 1.1.2 1.1.2 Built-in Multiplier/Accumulator ---------------------------------------------------------------------- 1-3 1.1.3 Built-in Single-precision FPU -------------------------------------------------------------------------------- 1-3 1.1.4 Built-in Flash Memory and RAM ---------------------------------------------------------------------------- 1-3 1.1.5 Built-in Clock Frequency Multiplier ------------------------------------------------------------------------- 1-4 1.1.6...
Page 7 CHAPTER 4 EIT 4.1 Outline of EIT --------------------------------------------------------------------------------------------------------------- 4-2 4.2 EIT Events ------------------------------------------------------------------------------------------------------------------ 4-3 4.2.1 Exception --------------------------------------------------------------------------------------------------------- 4-3 4.2.2 Interrupt ----------------------------------------------------------------------------------------------------------- 4-5 4.2.3 Trap ---------------------------------------------------------------------------------------------------------------- 4-6 4.3 EIT Processing Procedure ---------------------------------------------------------------------------------------------- 4-6 4.4 EIT Processing Mechanism --------------------------------------------------------------------------------------------- 4-7 4.5 Acceptance of EIT Events ----------------------------------------------------------------------------------------------- 4-8 4.6 Saving and Restoring the PC and PSW ----------------------------------------------------------------------------- 4-8 4.7 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 4-10 4.8 Exception Processing ---------------------------------------------------------------------------------------------------- 4-11...
Page 8 6.4.2 Flash Status Registers ---------------------------------------------------------------------------------------- 6-5 6.4.3 Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-5 6.4.4 Flash Control Registers --------------------------------------------------------------------------------------- 6-7 6.4.5 Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-11 6.5 Programming the Internal Flash Memory ---------------------------------------------------------------------------- 6-12 6.5.1 Outline of Internal Flash Memory Programming -------------------------------------------------------- 6-12 6.5.2 Controlling Operation Modes during Flash Programming -------------------------------------------- 6-17 6.5.3...
Page 9 9.2.4 DMA Destination Address Registers ---------------------------------------------------------------------- 9-20 9.2.5 DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21 9.2.6 DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22 9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27 9.3.1 DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27 9.3.2 DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33 9.3.3 Starting DMA ---------------------------------------------------------------------------------------------------- 9-34 9.3.4...
Page 10 10.4.10 Operation in TIO Noise Processing Input Mode -------------------------------------------------------- 10-116 10.4.11 Operation in TIO PWM Output Mode ---------------------------------------------------------------------- 10-117 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ----------------------- 10-120 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ----------- 10-122 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ----------------------- 10-124 10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-126 10.5.1...
Page 11 CHAPTER 11 A-D CONVERTERS 11.1 Outline of A-D Converters --------------------------------------------------------------------------------------------- 11-2 11.1.1 Conversion Modes --------------------------------------------------------------------------------------------- 11-6 11.1.2 Operation Modes ----------------------------------------------------------------------------------------------- 11-6 11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-9 11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-12 11.1.5 Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-12 11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-13 11.2.1 A-D Single Mode Registers 0 ------------------------------------------------------------------------------- 11-16...
Page 12 12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-32 12.4.1 Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-32 12.4.2 Starting CSIO Reception ------------------------------------------------------------------------------------- 12-34 12.4.3 Processing at End of CSIO Reception -------------------------------------------------------------------- 12-34 12.4.4 About Successive Reception -------------------------------------------------------------------------------- 12-35 12.4.5 Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-36 12.4.6 Example of CSIO Receive Operation --------------------------------------------------------------------- 12-37 12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-39...
Page 13 13.3.3 CAN Controller Error States --------------------------------------------------------------------------------- 13-74 13.4 Initializing the CAN Module -------------------------------------------------------------------------------------------- 13-75 13.4.1 Initializing the CAN Module ---------------------------------------------------------------------------------- 13-75 13.5 Transmitting Data Frames --------------------------------------------------------------------------------------------- 13-78 13.5.1 Data Frame Transmit Procedure --------------------------------------------------------------------------- 13-78 13.5.2 Data Frame Transmit Operation ---------------------------------------------------------------------------- 13-79 13.5.3 Transmit Abort Function -------------------------------------------------------------------------------------- 13-80 13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------ 13-81...
Page 14 16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2 16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4 16.2.1 CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4 16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6 CHAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2 17.2 Example of RAM Backup when Power is Down ----------------------------------------------------------------------- 17-3 17.2.1 Normal Operating State --------------------------------------------------------------------------------------- 17-3...
Page 15 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings ------------------------------------------------------------------------------------------- 21-2 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ---------------------------------------------- 21-3 21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) ------------------- 21-3 21.2.2 D.C.
Page 16 Appendix 4.1 Precautions about the CPU -------------------------------------------------------------------------- Appendix 4-2 Appendix 4.1.1 Precautions Regarding Data Transfer ------------------------------------------------ Appendix 4-2 Appendix 4.2 Precautions about the Address Space ------------------------------------------------------------------ Appendix 4-3 Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------- Appendix 4-3 Appendix 4.3 Precautions about EIT ------------------------------------------------------------------------------------ Appendix 4-3 Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory -------------------------- Appendix 4-3 Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------------------- Appendix 4-4 Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------- Appendix 4-4...
Page 17 This page is blank for reasons of layout. (12)
Page 18: Chapter 1 Overview
CHAPTER 1 OVERVIEW Outline of the 32180 Group Block Diagram Pin Functions Pin Assignments...
Page 19: M32R Family Cpu Core With Built-In Fpu (M32R-Fpu)
1.1 Outline of the 32180 Group 1.1 Outline of the 32180 Group The 32180 group (hereafter simply the 32180) belongs to the M32R/ECU series in the M32R family of Mitsubishi microcomputers. For details about the current development status of the 32180, please contact your nearest office of Mitsubishi or its distributor.
Page 20: Built-In Multiplier/Accumulator
OVERVIEW 1.1 Outline of the 32180 Group 1.1.2 Built-in Multiplier/Accumulator (1) Built-in high-speed multiplier • The M32R-FPU contains a 32 bits × 16 bits high-speed multiplier which enables the M32R-FPU to execute a 32 bits × 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable sum-of-products instructions •...
Page 21: Built-In Clock Frequency Multiplier
OVERVIEW 1.1 Outline of the 32180 Group 1.1.5 Built-in Clock Frequency Multiplier • The 32180 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below. CPUCLK (CPU clock) XIN pin (64MHz-80MHz) (8MHz-10MHz) BCLK (peripheral clock) (16MHz-20MHz) Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock Functional Block Features...
Page 22: Block Diagram
OVERVIEW 1.2 Block Diagram 1.2 Block Diagram Figure 1.2.1 shows a block diagram of the 32180. The features of each block are described in Table 1.2.1. Internal Bus M32R-FPU Core Interface (80 MHz) DMAC Multiplier/Accumulator (32 bits × 16 bits + 56 bits) (10 channels) Single-precision FPU (fully IEEE 754 compliant)
Page 23 OVERVIEW 1.2 Block Diagram Table 1.2.1 Features of the 32180 (1/2) Functional Block Features M32R-FPU CPU core • Implementation: Five-stage pipelined instruction processing (processed in six stages when performing floating-point arithmetic) • Internal 32-bit structure of the core • Register configuration General-purpose registers: 32 bits ×...
Page 24 OVERVIEW 1.2 Block Diagram Table 1.2.1 Features of the 32180 (2/2) Functional Block Features A-D converter (ADC) • 16 channels: 10-bit resolution A-D converter × 2 blocks • Conversion modes: Ordinary conversion modes plus comparator mode • Operation modes: Single conversion mode and n-channel scan mode (n = 1–16) •...
Page 25: Pin Functions
OVERVIEW 1.3 Pin Functions 1.3 Pin Functions Figure 1.3.1 shows the 32180’s pin function diagram. Pin functions are described in Table 1.3.1. P93/TO16-P97/TO20 Port 9 XOUT P100/TO8 Serial I/O Clock VCNT P101/TO9/TXD3 Port 10 OSC-VCC P102/TO10/CTX1 OSC-VSS P103/TO11-P107/TO15 Reset RESET# P110/TO0-P117/TO7 Port 11 MOD0...
Page 26 OVERVIEW 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (1/5) Type Pin Name Signal Name Input/Output Description Power supply VCCE Main power supply – Power supply for the device (5.0 V ± 0.5 V or 3.3 V ± 0.3 V). EXCVCC Internal power supply –...
Page 27 OVERVIEW 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (2/5) Type Pin Name Signal Name Input/Output Description Data bus DB0–DB15 Data bus Input/output This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined.
Page 28 OVERVIEW 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (3/5) Type Pin Name Signal Name Input/Output Description A-D converter AVCC0, Analog power supply – AVCC0 and AVCC1 are the power supply for the A-D0 and AVCC1 the A-D1 converter, respectively. Connect AVCC0 and AVCC1 to the power supply rail.
Page 29 OVERVIEW 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (4/5) Type Pin Name Signal Name Input/Output Description Serial I/O TXD0 Transmit data Output Transmit data output pin for serial I/O channel 0. RXD0 Received data Input Received data input pin for serial I/O channel 0. TXD1 Transmit data Output...
Page 30 OVERVIEW 1.3 Pin Functions Table 1.3.1 Description of Pin Functions (5/5) Type Pin Name Signal Name Input/Output Description Input/output P00–P07 Input/output port 0 Input/output Programmable input/output port. ports P10–P17 Input/output port 1 (Note 1) P20–P27 Input/output port 2 P30–P37 Input/output port 3 P41–P47 Input/output port 4 P61–P63...
Page 31: Pin Assignments
OVERVIEW 1.4 Pin Assignments 1.4 Pin Assignments Figure 1.4.1 shows the 32180’s pin assignment diagram. A pin assignment table is shown in Table 1.4.1. P174/TXD2 P97/TO20 P175/RXD2 P117/TO7 P176/TXD3 P116/TO6 P177/RXD3 P115/TO5 P173/TIN25 P114/TO4 P172/TIN24 P113/TO3 P112/TO2 MOD0 P111/TO1 MOD1 P110/TO0 EXCVDD P147/TIN15...
Page 32 OVERVIEW 1.4 Pin Assignments The pins directed for input go to a high-impedance state (Hi-z) when reset. The term “when reset” means that input on RESET# pin is held low (the device remains reset), and that the RESET# pin is released back high (the device comes out of reset).
Page 33 OVERVIEW 1.4 Pin Assignments Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (2/6) Function Pin State When Reset Symbol Type Condition Other than Other than State during State at reset Port Function Type port port reset release JTCK (Note 1) JTCK Input JTCK Input...
Page 34 OVERVIEW 1.4 Pin Assignments Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (3/6) Function Pin State When Reset Symbol Type Condition Other than Other than State during State at reset Port Function Type port port reset release 101 P195/TIN31 P195 TIN31 Input/output P195 Input...
Page 35 OVERVIEW 1.4 Pin Assignments Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (4/6) Function Pin State When Reset Symbol Type Condition Other than Other than State during State at reset Port Function Type port port reset release During single-chip and Input Hi-z Hi-z external extension modes...
Page 36 OVERVIEW 1.4 Pin Assignments Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (5/6) Function Pin State When Reset Symbol Type Condition Other than Other than State during State at reset Port Function Type port port reset release 176 P86/RXD1 RXD1 Input/output Input Hi-z Hi-z...
Page 37 OVERVIEW 1.4 Pin Assignments Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (6/6) Function Pin State When Reset Symbol Type Condition Other than Other than State during State after Port Function Type port port reset reset During single-chip and Input Hi-z Hi-z external extension modes 211 P01/DB1...
Page 38: Chapter 2 Cpu
CHAPTER 2 CPU Registers General-purpose Registers Control Registers Accumulator Program Counter Data Formats Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution Precautions on CPU...
Page 39 2.1 CPU Registers 2.1 CPU Registers The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration. 2.2 General-purpose Registers The 16 general-purpose registers (R0–R15) are of 32-bit width and are used to retain data and base address, as well as for integer calculations, floating-point operations, etc.
Page 40: Processor Status Word Register: Psw (Cr0)
2.3 Control Registers 2.3.1 Processor Status Word Register: PSW (CR0) BPSW field PSW field <After reset: B’0000 0000 0000 0000 ??00 000? 0000 0000> Bit Name Function 0–15 No function assigned. Fix to "0". Saves value of SM bit when EIT occurs Backup SM Bit Saves value of IE bit when EIT occurs Backup IE Bit...
Page 41: Condition Bit Register: Cbr (Cr1)
2.3 Control Registers 2.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register’s C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) After reset, the value of CBR is H’0000 0000.
Page 42: Floating-Point Status Register: Fpsr (Cr7)
2.3 Control Registers 2.3.5 Floating-point Status Register: FPSR (CR7) <After reset: H’0000 0100> Bit Name Function Reflects the logical sum of FU, FZ, FO and FV. – Floating-point Exception Summary Bit Set to "1" when an inexact exception occurs (if EIT processing is Inexact Exception Flag unexecuted (Note 1)).
Page 43 2.3 Control Registers 0: No underflow exception occurred (Note 3) Underflow Exception Cause Bit 1: An underflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No zero divide exception occurred. (Note 3) Zero Divide Exception Cause Bit 1: A zero divide exception occurred.
Page 44: Accumulator
2.4 Accumulator 2.4 Accumulator The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction “MUL,”...
Page 45: Data Formats
2.6 Data Formats 2.6 Data Formats 2.6.1 Data Types The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2’s complements. Signed byte (8-bit) integer Unsigned byte...
Page 46 2.6 Data Formats 2.6.2 Data Formats (1) Data formats in registers The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register.
Page 47 2.6 Data Formats (2) Data formats in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively.
Page 48 2.6 Data Formats Mitsubishi 7700 and M16C families M32R family microcomputer family name Endian Little/little Little/big Big/big (bit/byte) Address Data arrangement Bit number 7–0 15–8 23–16 31–24 31–24 23–16 15–8 7–0 0–7 8–15 16–23 24–31 Example: .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 0x01234567 Note: •...
Page 49 2.6 Data Formats (5) Transfer from memory (signed) to registers Memory Register • Signed 32 bits label Rdest LD24 Rsrc, #label Rdest, @Rsrc • Signed 16 bits label Rdest LD24 Rsrc, #label LDH Rdest, @Rsrc Determined by MSB 0: Positive number 1: Negative number •...
Page 50 2.6 Data Formats (7) Notes on data transfer When transferring data, be aware that data arrangements in registers and memory are different. Data in registers Data in memory • Word data (32 bits) (R0–R15) • Halfword data (16 bits) (R0–R15) (R0–R15) •...
Page 51: Supplementary Explanation For Bset, Bclr, Lock And Unlock Instruction Execution
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR instruction finishes.
Page 52: Chapter 3 Address Space
CHAPTER 3 ADDRESS SPACE Outline of the Address Space Operation Modes Internal ROM and Extended External Areas Internal RAM and SFR Areas EIT Vector Entry ICU Vector Table Notes on Address Space...
Page 53 ADDRESS SPACE 3.1 Outline of the Address Space 3.1 Outline of the Address Space The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R/ECU consists of the following: (1) User space •...
Page 54 ADDRESS SPACE 3.1 Outline of the Address Space EIT vector entry Logical address H'0000 0000 H'0000 0000 Internal ROM area 1 Mbytes 16 Mbytes (Note 1) H'000F FFFF H'0010 0000 CS0 area H'001F FFFF H'0020 0000 CS1 area User space H'003F FFFF 2 Gbytes H'0040 0000...
Page 55 ADDRESS SPACE 3.2 Operation Modes 3.2 Operation Modes The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.5, “Programming the Internal Flash Memory.”...
Page 56: Operation Modes
ADDRESS SPACE 3.3 Internal ROM and Extended External Areas 3.3 Internal ROM and Extended External Areas The 8-Mbyte area in the user space from the address H’0000 0000 to the address H’007F FFFF comprise the internal ROM and extended external areas. For the address mapping of these areas that differs with each opera- tion mode, see Section 3.2, “Operation Modes.”...
Page 57: Internal Ram And Sfr Areas
ADDRESS SPACE 3.4 Internal RAM and SFR Areas 3.4 Internal RAM and SFR Areas The 8-Mbyte area from the address H’0080 0000 to the address H’00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area from the address H’0080 0000 to the address H’0081 FFFF.
Page 58 ADDRESS SPACE 3.4 Internal RAM and SFR Areas +0 address +1 address +0 address +1 address H'0080 0000 H'0080 078C MJT(TID0) Interrupt Controller H'0080 078E Multijunction H'0080 0790 (ICU) timer (MJT) MJT(TOU0) H'0080 007E H'0080 07E2 H'0080 0080 A-D0 Converter H'0080 00EE H'0080 0A00 H'0080 0100...
Page 59 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (1/27) Address +0 address +1 address See pages b7 b8 H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 (Use inhibited area) H'0080 0004 Interrupt Request Mask Register (Use inhibited area) (IMASK) H'0080 0006 SBI Control Register (SBICR)
Page 60 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (2/27) Address +0 address +1 address See pages b7 b8 H'0080 009C 10-bit A-D0 Data Register 6 11-31 (AD0DT6) H'0080 009E 10-bit A-D0 Data Register 7 11-31 (AD0DT7) H'0080 00A0 10-bit A-D0 Data Register 8 11-31...
Page 61 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (3/27) Address +0 address +1 address See pages b7 b8 H'0080 0116 SIO0 Receive Control Register SIO0 Baud Rate Register 12-20 (S0RCNT) (S0BAUR) 12-23 (Use inhibited area) H'0080 0120 SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register 12-14...
Page 62 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (4/27) Address +0 address +1 address See pages b7 b8 H'0080 0204 Prescaler Register 2 Output Event Bus Control Register 10-12 (PRS2) (OEBCR) 10-17 (Use inhibited area) H'0080 0210 TCLK Input Processing Control Register 10-20 (TCLKCR)
Page 63 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (5/27) Address +0 address +1 address See pages b7 b8 H'0080 0260 TOP2 Counter 10-75 (TOP2CT) H'0080 0262 TOP2 Reload Register 10-76 (TOP2RL) H'0080 0264 (Use inhibited area) H'0080 0266 TOP2 Correction Register 10-77...
Page 64 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (6/27) Address +0 address +1 address See pages b7 b8 H'0080 02C0 TOP8 Counter 10-75 (TOP8CT) H'0080 02C2 TOP8 Reload Register 10-76 (TOP8RL) H'0080 02C4 (Use inhibited area) H'0080 02C6 TOP8 Correction Register 10-77...
Page 65 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (7/27) Address +0 address +1 address See pages b7 b8 H'0080 0324 TIO2 Reload 1 Register 10-111 (TIO2RL1) H'0080 0326 TIO2 Reload 0/ Measure Register 10-110 (TIO2RL0) (Use inhibited area) H'0080 0330 TIO3 Counter 10-109...
Page 66 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (8/27) Address +0 address +1 address See pages b7 b8 H'0080 0386 TIO8 Reload 0/ Measure Register 10-110 (TIO8RL0) H'0080 0388 (Use inhibited area) H'0080 038A TIO8 Control Register TIO9 Control Register 10-108 (TIO8CR)
Page 67 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (9/27) Address +0 address +1 address See pages b7 b8 H'0080 03FC TML0 Measure 0 Register (Upper) 10-135 (TML0MR0) H'0080 03FE (Lower) H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-24 (DM04ITST)
Page 68 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (10/27) Address +0 address +1 address See pages b7 b8 H'0080 044A DMA8 Source Address Register 9-19 (DM8SA) H'0080 044C DMA8 Destination Address Register 9-20 (DM8DA) H'0080 044E DMA8 Transfer Count Register 9-21 (DM8TCT)
Page 69 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (11/27) Address +0 address +1 address See pages b7 b8 H'0080 0720 P0 Direction Register P1 Direction Register (P0DIR) (P1DIR) H'0080 0722 P2 Direction Register P3 Direction Register (P2DIR) (P3DIR) H'0080 0724...
Page 70 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (12/27) Address +0 address +1 address See pages b7 b8 H'0080 0780 PWM Output 0 Disable Control Register PWM Output 0 Disable Level Control Register 10-174 (PO0DISCR) (PO0LVCR) 10-177 H'0080 0782 PWM Output 1 Disable Control Register...
Page 71 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (13/27) Address +0 address +1 address See pages b7 b8 H'0080 07C4 TOU0_6 Reload Register TOU0_6 Reload 1 Register 10-164 (TOU06RLW) (TOU06RL1) 10-167 H'0080 07C6 TOU0_6 Reload 0 Register 10-166 (TOU06RL0) H'0080 07C8...
Page 72 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (14/27) Address +0 address +1 address See pages b7 b8 H'0080 0A8A A-D1 Disconnection Detection Assist Method Select Register 11-26 (AD1DDASEL) H'0080 0A8C A-D1 Comparate Data Register 11-30 (AD1CMP) H'0080 0A8E (Use inhibited area)
Page 73 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (15/27) Address +0 address +1 address See pages b7 b8 H'0080 0AEE (Use inhibited area) 8-bit A-D1 Data Register 15 11-32 (AD18DT15) (Use inhibited area) H'0080 0B8C TID1 Counter 10-144 (TID1CT) H'0080 0B8E...
Page 74 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (16/27) Address +0 address +1 address See pages b7 b8 H'0080 0BCC TOU1_7 Reload Register TOU1_7 Reload 1 Register 10-164 (TOU17RLW) (TOU17RL1) 10-167 H'0080 0BCE TOU1_7 Reload 0 Register 10-166 (TOU17RL0) H'0080 0BD0...
Page 75 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (17/27) Address +0 address +1 address See pages b7 b8 H'0080 0CB8 TOU2_5 Counter (Upper) 10-161 (TOU25CTW) (TOU25CTH) H'0080 0CBA (Lower) 10-163 (TOU25CT) H'0080 0CBC TOU2_5 Reload Register TOU2_5 Reload 1 Register 10-164 (TOU25RLW)
Page 76 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (18/27) Address +0 address +1 address See pages b7 b8 H'0080 0FFC TML1 Measure 0 Register (Upper) 10-135 (TML1MR0) H'0080 0FFE (Lower) (Use inhibited area) H'0080 1000 CAN0 Control Register 13-15 (CAN0CNT) H'0080 1002...
Page 77 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (19/27) Address +0 address +1 address See pages b7 b8 H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-53 (C0MSL2CNT) (C0MSL3CNT) H'0080 1054 CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register 13-53...
Page 78 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (20/27) Address +0 address +1 address See pages b7 b8 H'0080 1136 CAN0 Message Slot 3 Data 0 CAN0 Message Slot 3 Data 1 13-63 (C0MSL3DT0) (C0MSL3DT1) 13-64 H'0080 1138 CAN0 Message Slot 3 Data 2 CAN0 Message Slot 3 Data 3...
Page 79 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (21/27) Address +0 address +1 address See pages b7 b8 H'0080 117C CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 13-69 (C0MSL7DT6) (C0MSL7DT7) 13-70 H'0080 117E CAN0 Message Slot 7 Timestamp 13-71...
Page 80 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (22/27) Address +0 address +1 address See pages b7 b8 H'0080 11C2 CAN0 Message Slot 12 Extended ID 0 CAN0 Message Slot 12 Extended ID 1 13-59 (C0MSL12EID0) (C0MSL12EID1) 13-60 H'0080 11C4...
Page 81 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (23/27) Address +0 address +1 address See pages b7 b8 H'0080 1406 CAN1 Configuration Register 13-22 (CAN1CONF) H'0080 1408 CAN1 Timestamp Count Register 13-24 (CAN1TSTMP) H'0080 140A CAN1 Receive Error Count Register CAN1 Transmit Error Count Register 13-25 (CAN1REC)
Page 82 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (24/27) Address +0 address +1 address See pages b7 b8 H'0080 145C CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register 13-53 (C1MSL12CNT) (C1MSL13CNT) H'0080 145E CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register 13-53...
Page 83 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (25/27) Address +0 address +1 address See pages b7 b8 H'0080 1540 CAN1 Message Slot 4 Standard ID 0 CAN1 Message Slot 4 Standard ID 1 13-57 (C1MSL4SID0) (C1MSL4SID1) 13-58 H'0080 1542...
Page 84 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (26/27) Address +0 address +1 address See pages b7 b8 H'0080 1586 CAN1 Message Slot 8 Data 0 CAN1 Message Slot 8 Data 1 13-63 (C1MSL8DT0) (C1MSL8DT1) 13-64 H'0080 1588 CAN1 Message Slot 8 Data 2 CAN1 Message Slot 8 Data 3...
Page 85 ADDRESS SPACE 3.4 Internal RAM and SFR Areas SFR Area Register Map (27/27) Address +0 address +1 address See pages b7 b8 H'0080 15CC CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 13-69 (C1MSL12DT6) (C1MSL12DT7) 13-70 H'0080 15CE CAN1 Message Slot 12 Timestamp 13-71...
Page 86: Eit Vector Entry
ADDRESS SPACE 3.5 EIT Vector Entry 3.5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/extended external areas. The branch instruc- tion for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here.
Page 87: Icu Vector Table
ADDRESS SPACE 3.6 ICU Vector Table 3.6 ICU Vector Table The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set.
Page 88 ADDRESS SPACE 3.6 ICU Vector Table ICU Vector Table Memory Map (2/2) Address +0 address +1 address H'0000 00D8 SIO0 Transmit Interrupt Handler Start Address (A0–A15) H'0000 00DA SIO0 Transmit Interrupt Handler Start Address (A16–A31) H'0000 00DC A-D0 Conversion Interrupt Handler Start Address (A0–A15) H'0000 00DE A-D0 Conversion Interrupt Handler Start Address (A16–A31) H'0000 00E0...
Page 89: Notes On Address Space
ADDRESS SPACE 3.7 Notes about Address Space 3.7 Notes about Address Space • Virtual flash emulation function The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the virtual flash emulation function.
Page 90: Chapter 4 Eit
CHAPTER 4 Outline of EIT EIT Events EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing 4.10 Trap Processing 4.11 EIT Priority Levels 4.12 Example of EIT Processing 4.13 Precautions on EIT...
Page 91 4.1 Outline of EIT 4.1 Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap).
Page 92: Eit Events
4.2 EIT Events 4.2 EIT Events 4.2.1 Exception (1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions.
Page 93 4.2 EIT Events 3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs.
Page 94: Interrupt
4.2 EIT Events 5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Table 4.2.6 Operation Results When an IVLD Occurred Operation Result (Content of the Destination Register) When the IVLD EIT Occurrence Condition...
Page 95: Trap
4.2 EIT Events 4.2.3 Trap Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0–15. 4.3 EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers).
Page 96: Eit Processing Mechanism
4.4 EIT Processing Mechanism 4.4 EIT Processing Mechanism The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/ Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register).
Page 97: Acceptance Of Eit Events
4.5 Acceptance of EIT Events 4.5 Acceptance of EIT Events When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below.
Page 98 4.6 Saving and Restoring the PC and PSW [1] Saving the SM, IE and C bits [3] Saving the PC ← ← ← ← [4] Setting the vector address in the PC ← Vector address [2] Updating the SM, IE and C bits ←...
Page 99 4.7 EIT Vector Entry 4.7 EIT Vector Entry The EIT vector entry is located in the user space beginning with the address H’0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address Reset Interrupt H'0000 0000 (Note 1) 0 Undefined...
Page 100: Exception Processing
4.8 Exception Processing 4.8 Exception Processing 4.8.1 Reserved Instruction Exception (RIE) [Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an exter- nal interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted.
Page 101: Address Exception (Ae)
4.8 Exception Processing (4) Branching to the EIT vector entry The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector entry to jump to the start address of the user-created handler.
Page 102: Floating-Point Exception (Fpe)
4.8 Exception Processing Address Address H ' 0 0 H ' 0 0 Return Return H ' 0 4 H ' 0 4 AE occurred AE occurred address address H ' 0 8 H ' 0 8 H ' 0 C H ' 0 C H ' 0 4 H ' 0 6...
Page 103 4.8 Exception Processing (3) Saving the PC The PC value of the instruction that generated the FPE exception + 4 is set in the BPC register. Because all of the instructions that generate an FPE exception are 32 bits long, the address to which the RTE returns is always the instruction next to the one that generated the FPE exception.
Page 104: Interrupt Processing
4.9 Interrupt Processing 4.9 Interrupt Processing 4.9.1 Reset Interrupt (RI) [Occurrence Conditions] A reset interrupt is unconditionally accepted in any machine cycle by pulling the RESET# input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register’s SM, IE and C bits are initialized as shown below.
Page 105 4.9 Interrupt Processing Order in which instructions are executed Address 1000 Address 1002 Address 1004 Address 1000 16-bit instruction 16-bit instruction 32-bit instruction × Interrupt may Interrupt cannot Interrupt may Interrupt may be accepted be accepted be accepted be accepted Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits...
Page 106: External Interrupt (Ei)
4.9 Interrupt Processing 4.9.3 External Interrupt (EI) An external interrupt is generated upon an interrupt request which is output by the microcomputer’s internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, “Interrupt Controller.” For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described.
Page 107: Trap Processing
4.9 Interrupt Processing (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. 4.10 Trap Processing 4.10.1 Trap [Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction.
Page 108: Eit Priority Levels
4.10 Trap Processing (4) Branching to the EIT vector entry The CPU branches to the addresses H’0000 0040–H’0000 007C in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H’0000 0040–H’0000 007C of the EIT vector entry to jump to the start address of the user-created handler.
Page 109: Example Of Eit Processing
4.12 Example of EIT Processing 4.12 Example of EIT Processing (1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly IE = 1 BPC register = Return address A IE = 0 RIE, AE, FPE, SBI, EI or TRAP If IE = 0, no events but reset and occurs singly SBI are accepted.
Page 110 4.12 Example of EIT Processing EIT vector entry BRA instruction (Other than SBI) (SBI) EIT handler PC→BPC Hardware Save BPC to the stack PSW→BPSW preprocessing (Note 1) Save PSW to the stack System Break Interrupt (SBI) processing Save general-purpose Program being registers to the stack executed EIT event...
Page 111: Precautions On Eit
4.13 Precautions on EIT 4.13 Precautions on EIT The Address Exception (AE) requires caution because if one of the instructions that use “register indirect + register update” addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined.
Page 112: Outline Of The Interrupt Controller
CHAPTER 5 INTERRUPT CONTROLLER (ICU) Outline of the Interrupt Controller ICU Related Registers Interrupt Request Sources in Internal Peripheral I/O ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt (SBI) Operation...
Page 113 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller 5.1 Outline of the Interrupt Controller The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI).
Page 114 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller Interrupt Controller System Break Interrupt (SBI) request generated (nonmaskable) SBI Control Register SBIREQ (SBICR) SBI# To the CPU core Peripheral circuits Edge Interrupt request IREQ External Interrupt (EI) ILEVEL Edge request generated Interrupt request IREQ (maskable)
Page 115 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2 ICU Related Registers The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map Address +0 address +1 address See pages b7 b8 H'0080 0000 Interrupt Vector Register (IVECT) H'0080 0002 (Use inhibited area)
Page 116: Interrupt Vector Register
INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.1 Interrupt Vector Register Interrupt Vector Register (IVECT) <Address: H’0080 0000> IVECT <After reset: Undefined> Bit Name Function IVECT When an interrupt request is accepted, the 16-low-order 16 low-order bits of ICU vector table address bits of the ICU vector table address for the accepted interrupt request source are stored in this register.
Page 117: Interrupt Request Mask Register
INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.2 Interrupt Request Mask Register Interrupt Request Mask Register (IMASK) <Address: H’0080 0004> IMASK <After reset: H’07> Bit Name Function 0–4 No function assigned. Fix to "0" 5–7 IMASK 000: Disable maskable interrupts Interrupt mask bit 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0–1...
Page 118: Sbi (System Break Interrupt) Control Register
INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.3 SBI (System Break Interrupt) Control Register SBI (System Break Interrupt) Control Register (SBICR) <Address: H’0080 0006> SBIREQ <After reset: H’00> Bit Name Function 0–6 No function assigned. Fix to "0" SBIREQ 0: SBI not requested R(Note 1) SBI request bit 1: SBI requested...
Page 119: Interrupt Control Registers
INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers 5.2.4 Interrupt Control Registers CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) <Address: H’0080 0060> TIN30–33 Input Interrupt Control Register (ITIN3033CR) <Address: H’0080 0061> TID2 Output Interrupt Control Register (ITID2CR) <Address: H’0080 0062> A-D1 Conversion Interrupt Control Register (IAD1CCR) <Address: H’0080 0063>...
Page 120 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers b15) IREQ ILEVEL <After reset: H’07> Bit Name Function 0–2 No function assigned. Fix to "0" (8–10) IREQ <When edge recognized> (11) Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request...
Page 121 INTERRUPT CONTROLLER (ICU) 5.2 ICU Related Registers Interrupt request from each internal peripheral I/O IREQ Bit 3 or 11 Data bus Set/clear Reset Interrupt enabled IVECT read IMASK write Clear Bits 5-7 or bits 13-15 ILEVEL Interrupt priority To the CPU core (levels 0-7) resolving circuit Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)
Page 122: Interrupt Request Sources In Internal Peripheral I/O
INTERRUPT CONTROLLER (ICU) 5.3 Interrupt Request Sources in Internal Peripheral I/O 5.3 Interrupt Request Sources in Internal Peripheral I/O The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described.
Page 123: Icu Vector Table
INTERRUPT CONTROLLER (ICU) 5.4 ICU Vector Table 5.4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 32-source interrupt requests are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses Interrupt Request Source ICU Vector Table Addresses...
Page 124: Description Of Interrupt Operation
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5 Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register.
Page 125 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation Table 5.5.1 Hardware Fixed Priority Levels Priority Interrupt Request Source ICU Vector Table Address ICU Type of Input Source High TIN3–6 input interrupt request H'0000 0094 – H'0000 0097 Level-recognized TIN20–29 input interrupt request H'0000 0098 –...
Page 126: Processing By Internal Peripheral I/O Interrupt Handlers
INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers (1) Branching to the interrupt handler Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware preprocessing as described in Section 4.3, “EIT Processing Procedure.” The EIT vector entry for External Interrupt (EI) is located at the address H’0000 0080.
Page 127 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation [10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing.
Page 128 INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation EI (External Interrupt) vector entry H'0000 0080 BRA instruction EI (External Interrupt) handler Hardware preprocessing Save BPC to the stack when EIT is accepted (Note 1) Save PSW to the stack Save general-purpose registers to the stack Program being executed...
Page 129: Description Of System Break Interrupt (Sbi) Operation
INTERRUPT CONTROLLER (ICU) 5.6 Description of System Break Interrupt (SBI) Operation 5.6 Description of System Break Interrupt (SBI) Operation 5.6.1 Acceptance of SBI System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer.
Page 130: Chapter 6 Internal Memory
CHAPTER 6 INTERNAL MEMORY Outline of the Internal Memory Internal RAM Internal Flash Memory Registers Associated with the Internal Flash Memory Programming the Internal Flash Memory Virtual Flash Emulation Function Connecting to A Serial Programmer Internal Flash Memory Protect Function Precautions To Be Taken when Rewriting the Internal Flash Memory...
Page 131: Internal Flash Memory
INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.1 Outline of the Internal Memory The 32180 internally contains the following types of memory: • 48-Kbyte RAM • 1-Mbyte (1,024-Kbyte) flash memory 6.2 Internal RAM Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM Item Specification...
Page 132 INTERNAL MEMORY 6.3 Internal Flash Memory Internal flash memory area of the M32180F8 (1,024 Kbytes) H'0000 0000 16KB Block 0 H'0000 4000 Block 1 Unequal blocks H'0000 6000 Block 2 H'0000 8000 32KB Block 3 H'0001 0000 64KB Block 4 H'0002 0000 64KB Block 5...
Page 133: Registers Associated With The Internal Flash Memory
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map Address +0 address +1 address See pages b7 b8 H'0080 01E0...
Page 134: Flash Status Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.2 Flash Status Registers There are two registers to indicate the status of the internal flash memory: Flash Status Register 1 (FSTAT1) located in the SFR area (H’0080 01E1) and Flash Status Register 2 (FSTAT2) included in the internal flash memory.
Page 135 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory This status register is included in the internal flash memory, and can be enabled for read by writing the Read Status command (H’7070) to any address of the internal flash memory. For details, see Section 6.5, “Program- ming the Internal Flash Memory.”...
Page 136: Flash Control Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.4 Flash Control Registers Flash Control Register 1 (FCNT1) <Address: H’0080 01E2> FENTRY FEMMOD <After reset: H’00> Bit Name Function 0–2 No function assigned. Fix to "0". FENTRY 0: Normal read Flash E/W enable mode entry bit 1: Program/erase enable 4–6...
Page 137 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Control Register 2 (FCNT2) <Address: H’0080 01E3> FPROT <After reset: H’00> Bit Name Function 8–14 No function assigned. Fix to "0". FPROT 0: Protection by lock bit effective Unlock bit 1: Protection by lock bit invalidated Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erase operation).
Page 138 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory Flash Control Register 3 (FCNT3) <Address: H’0080 01E4> FELEVEL <After reset: H’00> Bit Name Function 0–6 No function assigned. Fix to "0". FELEVEL 0: Normal level Erase margin-up bit 1: Raise erase margin up Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands.
Page 139 INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory FENTRY = 0 FENTRY = 1 Program/erase the flash memory * At this point in time, the FSTAT1 register FSTAT bit = 1 (ready). Error found Programming/erase operation terminated normally FRESET = 1 FRESET = 0 Program/erase...
Page 140: Virtual Flash S Bank Registers
INTERNAL MEMORY 6.4 Registers Associated with the Internal Flash Memory 6.4.5 Virtual Flash S Bank Registers Virtual Flash S Bank Register 0 (FESBANK0) <Address: H’0080 01E8> Virtual Flash S Bank Register 1 (FESBANK1) <Address: H’0080 01EA> Virtual Flash S Bank Register 2 (FESBANK2) <Address: H’0080 01EC>...
Page 141: Programming The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5 Programming the Internal Flash Memory 6.5.1 Outline of Internal Flash Memory Programming To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "high", MOD0 = "high"...
Page 142 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode.
Page 143 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Reset signal deasserted Reset signal deasserted (Boot program starts) Mode Mode POWER ON selected selected RESET# pin MOD0 pin MOD1 pin FP pin Settings by the boot program FENTRY bit Flash programming/erasing by the boot program Figure 6.5.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it) 6-14...
Page 144 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory.
Page 145 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Flash mode Flash mode Flash rewrite turned on turned off starts RESET# pin High or low MOD0 pin MOD1 pin High or low (single-chip or external extension) FP pin High or low FENTRY bit Flash programming/erasing by the flash write/erase program...
Page 146: Controlling Operation Modes During Flash Programming
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.2 Controlling Operation Modes during Flash Programming The microcomputer’s operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory.
Page 147: P8 Data Register
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.3 P8 Data Register P8 Data Register (P8DATA) <Address: H’0080 0708> MOD0DT MOD1DT P82DT P83DT P84DT P85DT P86DT P87DT <After reset: Undefined> Bit Name Function MOD0DT 0: MOD0 pin = "low" – MOD0 data bit 1: MOD0 pin = "high"...
Page 148 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Enter one of the following modes: • Single-chip mode • Boot mode • External extension mode FMOD(H'0080 01E0) FPMOD P8DATA(H'0080 0708) D0 = MOD0DT D1 = MOD1DT Check MOD0/1 and FP pin levels Transfer the flash write/erase program into the internal RAM...
Page 149: Procedure For Programming/Erasing The Internal Flash Memory
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed.
Page 150 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (2) Page Program command The internal flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H’00 to H’FF). To program the flash memory, write the Page Program command (H’4141) to any address of the internal flash memory and then the program data to the address to be programmed.
Page 151 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (3) Lock Bit Program command The internal flash memory can be protected against programming/erase operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H’7777) to any address of the internal flash memory.
Page 152 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory START Write the Lock Bit Program command (H'7777) to any address of the internal flash memory Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected Lock bit is programmed by Lock Bit Program (Note 1) Wait for 1 µs...
Page 153 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (4) Block Erase command The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the Block Erase command (H’2020) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to the last even address of the flash memory block to be erased (see Table 6.5.3, “M32180F8 Target Blocks and Specified Addresses”).
Page 154 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (5) Erase All Unlocked Blocks command The Erase All Unlocked Blocks command erases all flash memory blocks that are not protected. To erase all unlocked blocks, write the command (H’A7A7) to any address of the internal flash memory. Next, write the Verify command (H’D0D0) to any address of the internal flash memory, and all unlocked memory blocks are thereby erased.
Page 155 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (6) Read Status command The Read Status command reads the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory programming or erase operation has terminated normally. To read Flash Status Register 2, write the Read Status command (H’7070) to any address of the internal flash memory.
Page 156 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory (8) Read Lock Bit Status command The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erase operation. Write the Read Lock Bit Status command (H’7171) to any address of the internal flash memory.
Page 157 INTERNAL MEMORY 6.5 Programming the Internal Flash Memory Lock Bit Status Register (FLBST) FLBST0 FLBST1 <After reset: Undefined> Bit Name Function No function assigned. – FLBST0 0: Protected – Lock bit 0 1: Not protected 2–8 No function assigned. – FLBST1 0: Protected –...
Page 158: Flash Programming Time (Reference)
INTERNAL MEMORY 6.5 Programming the Internal Flash Memory 6.5.5 Flash Programming Time (Reference) The following shows the time needed to program internal flash memory for reference. (1) Time required for transfer by SIO (for a transfer data size of 1,024 KB) 1/57,600 bps ×...
Page 159: Virtual Flash Emulation Function
INTERNAL MEMORY 6.6 Virtual Flash Emulation Function 6.6 Virtual Flash Emulation Function The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function.
Page 160: Virtual Flash Emulation Area
INTERNAL MEMORY 6.6 Virtual Flash Emulation Function 6.6.1 Virtual Flash Emulation Area The following shows the internal flash memory areas in which the Virtual Flash Emulation Function is useful. Using the Virtual Flash S Bank Register (FESBANK0–FESBANK7), select one among all S banks of internal flash memory that are divided in 4-Kbyte units (by setting the eight start address bits A12–A19 of the desired S bank in the Virtual Flash S Bank Register SBANKAD bits).
Page 161 INTERNAL MEMORY 6.6 Virtual Flash Emulation Function <Internal flash> H'0000 0000 S bank 0 <Internal RAM> (4 Kbytes) H'0080 4000 H'0000 1000 S bank 1 (4 Kbytes) H'0000 2000 S bank 2 (4 Kbytes) H'0080 8000 4 Kbytes H'0080 9000 4 Kbytes H'0080 A000 4 Kbytes...
Page 162: Entering Virtual Flash Emulation Mode
INTERNAL MEMORY 6.6 Virtual Flash Emulation Function 6.6.2 Entering Virtual Flash Emulation Mode To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1". After entering virtual flash emulation mode, set the Virtual Flash S Bank Register MODENS bit to "1" to enable the Virtual Flash Emulation Function.
Page 163: Application Example Of Virtual Flash Emulation Mode
INTERNAL MEMORY 6.6 Virtual Flash Emulation Function 6.6.3 Application Example of Virtual Flash Emulation Mode By using two RAM areas that have been set in the same flash area by the Virtual Flash Emulation Function, the data in the flash memory can be replaced successively. (1) Operation when reset Flash memory Bank xx...
Page 164 INTERNAL MEMORY 6.6 Virtual Flash Emulation Function (4) Programming operation using RAM block 1 Flash memory Replaced Bank xx Initial value RAM block 1 Bank xx specified (Bank specification cleared) RAM block 0 Data write to RAM0 RAM block 1 (5) Programming operation switched from RAM block 1 to RAM block 0 Flash memory Replaced...
Page 165: Connecting To A Serial Programmer
INTERNAL MEMORY 6.7 Connecting to A Serial Programmer 6.7 Connecting to A Serial Programmer For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below.
Page 166 INTERNAL MEMORY 6.7 Connecting to A Serial Programmer The diagram below shows an example of a user system configuration which has had a serial programmer con- nected. After the user system is powered on, the serial programmer writes to the internal flash memory in clock- synchronized serial mode.
Page 167: Internal Flash Memory Protect Function
INTERNAL MEMORY 6.8 Internal Flash Memory Protect Function 6.8 Internal Flash Memory Protect Function The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emu- lator, the ID entered by a tool and the ID stored in the internal flash memory are collated.
Page 168: Precautions To Be Taken When Rewriting The Internal Flash Memory
INTERNAL MEMORY 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory The following describes precautions to be taken when programming/erasing the internal flash memory. • When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes.
Page 169 INTERNAL MEMORY 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory This page is blank for reasons of layout. 6-40 32180 Group User’s Manual (Rev.1.0)
Page 170: Chapter 7 Reset
CHAPTER 7 RESET Outline of Reset Reset Operation Internal State Immediately after Reset Things to Be Considered after Reset...
Page 171 RESET 7.1 Outline of Reset 7.1 Outline of Reset The microcomputer is reset by applying a low-level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry.
Page 172: Reset At Power-On
RESET 7.2 Reset Operation 7.2.1 Reset at Power-on When powering on the microcomputer, hold the RESET# signal input pin low until the rated power supply volt- age is reached and the microcomputer’s internal x8 clock generator becomes oscillating stably. 7.2.2 Reset during Operation To reset the microcomputer during operation, hold the RESET# signal input pin low for more than 200 ns.
Page 173: Internal State Immediately After Reset
RESET 7.3 Internal State Immediately after Reset 7.3 Internal State Immediately after Reset The table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described.
Page 174: Outline Of Input/Output Ports
CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS Outline of Input/Output Ports Selecting Pin Functions Input/Output Port Related Registers Port Input Level Switching Function Port Peripheral Circuits Precautions on Input/Output Ports...
Page 175 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.1 Outline of Input/Output Ports The 32810 has a total of 158 input/output ports from P0 to P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line.
Page 176 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions 8.2 Selecting Pin Functions Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers.
Page 177 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.2 Selecting Pin Functions DB10 DB11 DB12 DB13 DB14 DB15 CPU operation mode settings (Note 1) BLW# / BHW# / CS0# CS1# BLE# BHE# (Reserved) SBI# SCLKI4 / SCLKI5 / (P61) (P62) (P63) (P67) SCLKO4 SCLKO5 (Note 3) BCLK /...
Page 178 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3 Input/Output Port Related Registers The input/output port related registers included in the microcomputer consists of the port data register, port direc- tion register and port operation mode register. Note that P5 is reserved for future use. The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/2) Address +0 address...
Page 179 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers Input/Output Port Related Register Map (2/2) Address +0 address +1 address See pages b7 b8 H'0080 0740 P0 Operation Mode Register P1 Operation Mode Register (P0MOD) (P1MOD) H'0080 0742 P2 Operation Mode Register P3 Operation Mode Register 8-10 (P2MOD)
Page 180: Port Data Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.1 Port Data Registers P0 Data Register (P0DATA) <Address: H’0080 0700> P1 Data Register (P1DATA) <Address: H’0080 0701> P2 Data Register (P2DATA) <Address: H’0080 0702> P3 Data Register (P3DATA) <Address: H’0080 0703> P4 Data Register (P4DATA) <Address: H’0080 0704>...
Page 181: Port Direction Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.2 Port Direction Registers P0 Direction Register (P0DIR) <Address: H’0080 0720> P1 Direction Register (P1DIR) <Address: H’0080 0721> P2 Direction Register (P2DIR) <Address: H’0080 0722> P3 Direction Register (P3DIR) <Address: H’0080 0723> P4 Direction Register (P4DIR) <Address: H’0080 0724>...
Page 182: Port Operation Mode Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.3 Port Operation Mode Registers P0 Operation Mode Register (P0MOD) <Address: H’0080 0740> P00MD P01MD P02MD P03MD P04MD P05MD P06MD P07MD <After reset: H’00> Bit Name Function P00MD 0: P00 Port P00 operation mode bit 1: DB0 P01MD...
Page 183 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P2 Operation Mode Register (P2MOD) <Address: H’0080 0742> P20MD P21MD P22MD P23MD P24MD P25MD P26MD P27MD <After reset: H’00> Bit Name Function P20MD 0: P20 Port P20 operation mode bit 1: A23 P21MD 0: P21...
Page 184 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P4 Operation Mode Register (P4MOD) <Address: H’0080 0744> P44MD P45MD P46MD P47MD <After reset: H’00> Bit Name Function 0–3 No function assigned. Fix to "0". P44MD 0: P44 Port P44 operation mode bit 1: CS0# P45MD 0: P45...
Page 185 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P7 Operation Mode Register (P7MOD) <Address: H’0080 0747> P70MD P71MD P72MD P73MD P74MD P75MD P76MD P77MD <After reset: H’00> Bit Name Function P70MD 0: P70 Port P70 operation mode bit 1: BCLK/WR# P71MD 0: P71...
Page 186 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P9 Operation Mode Register (P9MOD) <Address: H’0080 0749> P93MD P94MD P95MD P96MD P97MD <After reset: H’00> Bit Name Function 8–10 No function assigned. Fix to "0". P93MD 0: P93 Port P93 operation mode bit 1: TO16 P94MD 0: P94...
Page 187 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P11 Operation Mode Register (P11MOD) <Address: H’0080 074B> P110MD P111MD P112MD P113MD P114MD P115MD P116MD P117MD <After reset: H’00> Bit Name Function P110MD 0: P110 Port P110 operation mode bit 1: TO0 P111MD 0: P111...
Page 188 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P13 Operation Mode Register (P13MOD) <Address: H’0080 074D> P130MD P131MD P132MD P133MD P134MD P135MD P136MD P137MD <After reset: H’00> Bit Name Function P130MD 0: P130 Port P130 operation mode bit 1: TIN16/PWMOFF0 (Note 1) P131MD 0: P131...
Page 189 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P15 Operation Mode Register (P15MOD) <Address: H’0080 074F> P150MD P151MD P152MD P153MD P154MD P155MD P156MD P157MD <After reset: H’00> Bit Name Function P150MD 0: P150 Port P150 operation mode bit 1: TIN0 P151MD 0: P151...
Page 190 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P17 Operation Mode Register (P17MOD) <Address: H’0080 0751> P172MD P173MD P174MD P175MD P176MD P177MD <After reset: H’00> Bit Name Function No function assigned. Fix to "0". P172MD 0: P172 Port P172 operation mode bit 1: TIN24 P173MD 0: P173...
Page 191 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P19 Operation Mode Register (P19MOD) <Address: H’0080 0753> P190MD P191MD P192MD P193MD P194MD P195MD P196MD P197MD <After reset: H’00> Bit Name Function P190MD 0: P190 Port P190 operation mode bit 1: TIN26 P191MD 0: P191...
Page 192 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers P21 Operation Mode Register (P21MOD) <Address: H’0080 0755> P210MD P211MD P212MD P213MD P214MD P215MD P216MD P217MD <After reset: H’00> Bit Name Function P210MD 0: P210 Port P210 operation mode bit 1: TO37 P211MD 0: P211...
Page 193: Port Peripheral Output Select Registers
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.4 Port Peripheral Output Select Registers P10 Peripheral Output Select Register (P10SMOD) <Address: H’0080 076A> P101 P102 <After reset: H’00> Bit Name Function No function assigned. Fix to "0". P101SMD 0: TO9 Port P101 peripheral output select mode bit 1: TXD3...
Page 194: Port Input Special Function Control Register
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers 8.3.5 Port Input Special Function Control Register Port Input Special Function Control Register (PICNT) <Address: H’0080 0745> XSTAT PISEL PIEN0 <After reset: H’00> Bit Name Function 8–10 No function assigned. Fix to "0". XSTAT 0: XIN oscillating R(Note 1)
Page 195 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers (1) To know whether XIN oscillation has ever stopped after being reset Read XSTAT (2) To know the current status of XIN oscillation Write XSTAT = 0 Wait before inspecting XSTAT Wait for 20 CPU clock periods or more Read XSTAT...
Page 196 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.3 Input/Output Port Related Registers (3) PIEN0 (Port input enable) bit (Bit 15) This bit is used to prevent current from flowing into the port input pins. Because the input/output ports are disabled against input after reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1".
Page 197: Port Input Level Switching Function
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function 8.4 Port Input Level Switching Function The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. Group 0: P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P70–P73, P224-P227 Group 1: P65–P67, P82–P87, P172–P177 Group 2: P160–P167, P210–P217...
Page 198 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function Port Group 0,1 Input Level Setting Register (PG01LEV) <Address: H’0080 0760> WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1 Port Group 2,3 Input Level Setting Register (PG23LEV) <Address: H’0080 0761> WF2SEL PT2SEL VT2SEL0 VT2SEL1 WF3SEL PT3SEL VT3SEL0 VT3SEL1 Port Group 4,5 Input Level Setting Register (PG45LEV) <Address: H’0080 0762>...
Page 199 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.4 Port Input Level Switching Function 0.7VCCE Schmitt 0.5VCCE Port input Input function enable 0.35VCCE PTnSEL CMOS Threshold VTnSELL Peripheral function Standard input level for each peripheral function pin input WFnSEL Figure 8.4.2 Port Level Switching Function 32180 Group User’s Manual (Rev.1.0) 8-26...
Page 200: Port Peripheral Circuits
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits 8.5 Port Peripheral Circuits Figures 8.5.1 through 8.5.4 show the peripheral circuit diagrams of the input/output ports described in the preced- ing pages. P00–P07(DB0–DB7) Direction register P10–P17(DB8–DB15) P20–P27(A23–A30) P30–P37(A15–A22) Data bus Port output latch P46, P47(A13, A14) P71(WAIT#)
Page 201 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits P101(TO9/TXD3) Direction register P102(TO10/CTX1) Port output latch Data bus Input data select bit Operation mode register (Note 1) Port level switching Peripheral output select register function (No peripheral input) Input function Peripheral function output 1 enable Peripheral function output 2...
Page 202 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits P160–P165(TO21–TO26) PWM output disable P180–P185(TO29–TO34) P210–P215(TO37–TO42) Direction register Port output latch Data bus Input data select bit Operation mode register (Note 1) Port level switching Peripheral function output function (No peripheral input) Input function enable P41(BLW#/BLE#)
Page 203 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.5 Port Peripheral Circuits SBI# Data bus P221(CRX0) (DB0–DB15) SBI#, CRX0 MOD0, MOD1 JTDI, JTCK, JTMS Output control JTDO RESET#, XIN, JTRST OSC-VCC, VCCE, VDDE VCC-BUS, EXCVCC, EXCVDD Notes: • The circle denotes a pin. •...
Page 204: Precautions On Input/Output Ports
INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.6 Precautions on Input/Output Ports 8.6 Precautions on Input/Output Ports • When using input/output ports in output mode Because the value of the Port Data Register is undefined after reset, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output.
Page 205 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.6 Precautions on Input/Output Ports This page is blank for reasons of layout. 32180 Group User’s Manual (Rev.1.0) 8-32...
Page 206: Chapter 9 Dmac
CHAPTER 9 DMAC Outline of the DMAC DMAC Related Registers Functional Description of the DMAC Precautions about the DMAC...
Page 207 DMAC 9.1 Outline of the DMAC 9.1 Outline of the DMAC The microcomputer internally contains a 10-channel DMAC (Direction Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O.
Page 208 DMAC 9.1 Outline of the DMAC Input event bus Output event bus 3 2 1 0 0 1 2 3 AD0 conversion completed AD0 conversion TIO8_udf completed TIN0S TIO8_udf DMA0 Software start TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf TIN13S Software start DMA1 CAN0_S1/S14 TID2_udf/ovf TIN18S...
Page 209 DMAC 9.2 DMAC Related Registers 9.2 DMAC Related Registers The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2) Address +0 address +1 address See pages b7 b8 H'0080 0400 DMA0–4 Interrupt Request Status Register DMA0–4 Interrupt Request Mask Register 9-24 (DM04ITST)
Page 210 DMAC 9.2 DMAC Related Registers DMAC Related Register Map (2/2) Address +0 address +1 address See pages b7 b8 H'0080 0440 DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 (DM3CNT0) (DM3CNT1) H'0080 0442 DMA3 Source Address Register 9-19 (DM3SA) H'0080 0444 DMA3 Destination Address Register...
Page 211: Dma Channel Control Registers
DMAC 9.2 DMAC Related Registers 9.2.1 DMA Channel Control Registers DMA0 Channel Control Register 0 (DM0CNT0) <Address: H’0080 0410> MDSEL0 TREQF0 REQSL0 TENL0 TSZSL0 SADSL0 DADSL0 <After reset: H’00> Bit Name Function MDSEL0 0: Normal mode DMA0 transfer mode select bit 1: Ring buffer mode TREQF0 0: Transfer not requested...
Page 212 DMAC 9.2 DMAC Related Registers DMA1 Channel Control Register 0 (DM1CNT0) <Address: H’0080 0420> SADSL1 DADSL1 MDSEL1 TREQF1 REQSL1 TENL1 TSZSL1 <After reset: H’00> Bit Name Function MDSEL1 0: Normal mode DMA1 transfer mode select bit 1: Ring buffer mode TREQF1 0: Transfer not requested R(Note 1)
Page 213 DMAC 9.2 DMAC Related Registers DMA2 Channel Control Register 0 (DM2CNT0) <Address: H’0080 0430> MDSEL2 TREQF2 REQSL2 TENL2 TSZSL2 SADSL2 DADSL2 <After reset: H’00> Bit Name Function MDSEL2 0: Normal mode DMA2 transfer mode select bit 1: Ring buffer mode TREQF2 0: Transfer not requested R(Note 1)
Page 214 DMAC 9.2 DMAC Related Registers DMA3 Channel Control Register 0 (DM3CNT0) <Address: H’0080 0440> MDSEL3 TREQF3 REQSL3 TENL3 TSZSL3 SADSL3 DADSL3 <After reset: H’00> Bit Name Function MDSEL3 0: Normal mode DMA3 transfer mode select bit 1: Ring buffer mode TREQF3 0: Transfer not requested R(Note 1)
Page 215 DMAC 9.2 DMAC Related Registers DMA4 Channel Control Register 0 (DM4CNT0) <Address: H’0080 0450> MDSEL4 TREQF4 REQSL4 TENL4 TSZSL4 SADSL4 DADSL4 <After reset: H’00> Bit Name Function MDSEL4 0: Normal mode DMA4 transfer mode select bit 1: Ring buffer mode TREQF4 0: Transfer not requested R(Note 1)
Page 216 DMAC 9.2 DMAC Related Registers DMA5 Channel Control Register 0 (DM5CNT0) <Address: H’0080 0418> MDSEL5 TREQF5 REQSL5 TENL5 TSZSL5 SADSL5 DADSL5 <After reset: H’00> Bit Name Function MDSEL5 0: Normal mode DMA5 transfer mode select bit 1: Ring buffer mode TREQF5 0: Transfer not requested R(Note 1)
Page 217 DMAC 9.2 DMAC Related Registers DMA6 Channel Control Register 0 (DM6CNT0) <Address: H’0080 0428> MDSEL6 TREQF6 REQSL6 TENL6 TSZSL6 SADSL6 DADSL6 <After reset: H’00> Bit Name Function MDSEL6 0: Normal mode DMA6 transfer mode select bit 1: Ring buffer mode TREQF6 0: Transfer not requested R(Note 1)
Page 218 DMAC 9.2 DMAC Related Registers DMA7 Channel Control Register 0 (DM7CNT0) <Address: H’0080 0438> MDSEL7 TREQF7 REQSL7 TENL7 TSZSL7 SADSL7 DADSL7 <After reset: H’00> Bit Name Function MDSEL7 0: Normal mode DMA7 transfer mode select bit 1: Ring buffer mode TREQF7 0: Transfer not requested R(Note 1)
Page 219 DMAC 9.2 DMAC Related Registers DMA8 Channel Control Register 0 (DM8CNT0) <Address: H’0080 0448> MDSEL8 TREQF8 REQSL8 TENL8 TSZSL8 SADSL8 DADSL8 <After reset: H’00> Bit Name Function MDSEL8 0: Normal mode DMA8 transfer mode select bit 1: Ring buffer mode TREQF8 0: Transfer not requested R(Note 1)
Page 220 DMAC 9.2 DMAC Related Registers DMA9 Channel Control Register 0 (DM9CNT0) <Address: H’0080 0458> MDSEL9 TREQF9 REQSL9 TENL9 TSZSL9 SADSL9 DADSL9 <After reset: H’00> Bit Name Function MDSEL9 0: Normal mode DMA9 transfer mode select bit 1: Ring buffer mode TREQF9 0: Transfer not requested R(Note 1)
Page 221 DMAC 9.2 DMAC Related Registers The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions.
Page 222 DMAC 9.2 DMAC Related Registers DMAn DMAn transfer Extended DMA transfer request source request source selected Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection 32180 Group User’s Manual (Rev.1.0) 9-17...
Page 223: Dma Software Request Generation Registers
DMAC 9.2 DMAC Related Registers 9.2.2 DMA Software Request Generation Registers DMA0 Software Request Generation Register (DM0SRI) <Address: H’0080 0460> DMA1 Software Request Generation Register (DM1SRI) <Address: H’0080 0462> DMA2 Software Request Generation Register (DM2SRI) <Address: H’0080 0464> DMA3 Software Request Generation Register (DM3SRI) <Address: H’0080 0466>...
Page 224: Dma Source Address Registers
DMAC 9.2 DMAC Related Registers 9.2.3 DMA Source Address Registers DMA0 Source Address Register (DM0SA) <Address: H’0080 0412> DMA1 Source Address Register (DM1SA) <Address: H’0080 0422> DMA2 Source Address Register (DM2SA) <Address: H’0080 0432> DMA3 Source Address Register (DM3SA) <Address: H’0080 0442> DMA4 Source Address Register (DM4SA) <Address: H’0080 0452>...
Page 225: Dma Destination Address Registers
DMAC 9.2 DMAC Related Registers 9.2.4 DMA Destination Address Registers DMA0 Destination Address Register (DM0DA) <Address: H’0080 0414> DMA1 Destination Address Register (DM1DA) <Address: H’0080 0424> DMA2 Destination Address Register (DM2DA) <Address: H’0080 0434> DMA3 Destination Address Register (DM3DA) <Address: H’0080 0444> DMA4 Destination Address Register (DM4DA) <Address: H’0080 0454>...
Page 226: Dma Transfer Count Registers
DMAC 9.2 DMAC Related Registers 9.2.5 DMA Transfer Count Registers DMA0 Transfer Count Register (DM0TCT) <Address: H’0080 0416> DMA1 Transfer Count Register (DM1TCT) <Address: H’0080 0426> DMA2 Transfer Count Register (DM2TCT) <Address: H’0080 0436> DMA3 Transfer Count Register (DM3TCT) <Address: H’0080 0446> DMA4 Transfer Count Register (DM4TCT) <Address: H’0080 0456>...
Page 227: Dma Interrupt Related Registers
DMAC 9.2 DMAC Related Registers 9.2.6 DMA Interrupt Related Registers The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software).
Page 228 DMAC 9.2 DMAC Related Registers Example for clearing interrupt request status Interrupt request status Initial state Interrupt request Event occurs on bit 6 Event occurs on bit 4 Write to the interrupt request status Only bit 6 cleared Bit 4 data retained Program example •...
Page 229 DMAC 9.2 DMAC Related Registers DMA0–4 Interrupt Request Status Register (DM04ITST) <Address: H’0080 0400> DMITST4 DMITST3 DMITST2 DMITST1 DMITST0 <After reset: H’00> Bit Name Function 0–2 No function assigned. Fix to "0". DMITST4 (DMA4 interrupt request status bit) 0: Interrupt not requested R(Note 1) DMITST3 (DMA3 interrupt request status bit) 1: Interrupt requested...
Page 230 DMAC 9.2 DMAC Related Registers DMA0–4 Interrupt Request Mask Register (DM04ITMK) <Address: H’0080 0401> DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0 <After reset: H’00> Bit Name Function 8–10 No function assigned. Fix to "0". DMITMK4 (DMA4 interrupt request mask bit) 0: Enable interrupt request DMITMK3 (DMA3 interrupt request mask bit) 1: Mask (disable) interrupt request DMITMK2 (DMA2 interrupt request mask bit)
Page 231 DMAC 9.2 DMAC Related Registers DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) DMA4UDF Data bus DMITST4 5-source inputs DMA transfer interrupt request 0 DMITMK4 (Level) DMA3UDF DMITST3 DMITMK3 DMA2UDF DMITST2 DMITMK2 DMA1UDF DMITST1 DMITMK1 DMA0UDF DMITST0 DMITMK0 Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0 DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) DMA9UDF...
Page 232: Functional Description Of The Dmac
DMAC 9.3 Functional Description of the DMAC 9.3 Functional Description of the DMAC 9.3.1 DMA Transfer Request Sources For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers on another DMA channel (cascade mode).
Page 233 DMAC 9.3 Functional Description of the DMAC Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1 REQSL1 DMA Transfer Request Source DMA Transfer Request Generation Timing Software start When any data is written to the DMA1 Software Request Generation Register MJT (output event bus 0) When MJT output event bus 0 signal is generated MJT (TIN13 input signal)
Page 234 DMAC 9.3 Functional Description of the DMAC Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3 REQSL3 DMA Transfer Request Source DMA Transfer Request Generation Timing Software start When any data is written to the DMA3 Software Request Generation Register Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty Serial I/O1 (reception completed) When serial I/O1 reception is completed Extended DMA3 transfer request...
Page 235 DMAC 9.3 Functional Description of the DMAC Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5 REQSL5 DMA Transfer Request Source DMA Transfer Request Generation Timing Software start or one DMA7 When any data is written to the DMA5 Software Request Generation Register transfer completed (software start) or when one DMA7 transfer is completed (cascade mode) All DMA0 transfers completed...
Page 236 DMAC 9.3 Functional Description of the DMAC Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7 REQSL7 DMA Transfer Request Source DMA Transfer Request Generation Timing Software start When any data is written to the DMA7 Software Request Generation Register Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty MJT (TIN2 input signal) When MJT TIN2 input signal is generated...
Page 237 DMAC 9.3 Functional Description of the DMAC Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9 REQSL9 DMA Transfer Request Source DMA Transfer Request Generation Timing Software start When any data is written to the DMA9 Software Request Generation Register Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty MJT (TIN8 input signal) When MJT TIN8 input signal is generated...
Page 238: Dma Transfer Processing Procedure
DMAC 9.3 Functional Description of the DMAC 9.3.2 DMA Transfer Processing Procedure Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0. DMA transfer processing starts Setting interrupt Set the interrupt controller's controller-related •...
Page 239: Starting Dma
DMAC 9.3 Functional Description of the DMAC 9.3.3 Starting DMA Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of DMA transfer request.
Page 240: Transfer Units
DMAC 9.3 Functional Description of the DMAC 9.3.6 Transfer Units Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer. 9.3.7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel.
Page 241 DMAC 9.3 Functional Description of the DMAC (5) Transfer count value The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). (6) Transfer byte positions When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus.
Page 242: End Of Dma And Interrupt
DMAC 9.3 Functional Description of the DMAC <When transfer size = 8 bits> <When transfer size = 16 bits> Transfer count Transfer address Transfer count Transfer address H'0080 1000 H'0080 1000 H'0080 1001 H'0080 1002 H'0080 1002 H'0080 1004 H'0080 101E H'0080 103C H'0080 101F H'0080 103E...
Page 243: Precautions About The Dmac
DMAC 9.4 Precautions about the DMAC 9.4 Precautions about the DMAC • About writing to the DMAC related registers Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag and the DMA Transfer Count Register that is protected in hardware.
Page 244: Chapter 10 Multijunction Timers
CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.2 Common Units of Multijunction Timers 10.3 TOP (Output-Related 16-Bit Timer) 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.5 TMS (Input-Related 16-Bit Timer) 10.6 TML (Input-Related 32-Bit Timer) 10.7 TID (Input-Related 16-Bit Timer) 10.8 TOU (Output-Related 24-Bit Timer)
Page 245 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers 10.1 Outline of Multijunction Timers The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs.
Page 246 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Table 10.1.2 Interrupt Generation Functions of MJT Signal Name MJT Interrupt Request Source Source of Interrupt No. of ICU Input Sources IRQ0 TIO0–3 output TIO0–3 output interrupt IRQ1 TOP6, TOP7 output TOP6, 7 output interrupt IRQ2 TOP0–5 output TOP0–5 output interrupt...
Page 247 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers DMA6 TIN1 input signal TOU0_1irq Common transfer request source (see Table 10.1.4) DMA7 TIN2 input signal TOU0_2irq Common transfer request source (see Table 10.1.4) DMA8 Input event bus 0 TIN7 input signal TOU0_6irq Common transfer request source (see Table 10.1.4) DMA9 TIN8 input signal...
Page 248 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 IRQ2 TOP 0 F/F0 TO0 (P110) IRQ2 TOP 1 F/F1 TO1 (P111) TCLK0 (P124) TCLK0S IRQ2 IRQ9...
Page 249 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TCLK3 (P127) TCLK3S TMS 0 IRQ7 cap3 cap2 cap1 cap0 IRQ10 TIN12 (P144) TIN12S IRQ10 TIN13 (P145)
Page 250 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Output event bus TIN16/PWMOFF0 PWMOFF0S PO0DOS IRQ13 (P130) TOU0_0 (24-bit) F/F21 TO21 (P160) DMA5 IRQ13 TOU0_1 (24-bit) F/F22 TO22 (P161) DMA6 IRQ13 F/F23 TOU0_2 (24-bit) TO23 (P162) DMA7 IRQ13 TOU0_3 (24-bit) F/F24 TO24 (P163) IRQ13 TOU0_4 (24-bit) F/F25...
Page 251 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers Input event bus Output event bus 3 2 1 0 0 1 2 3 AD0 conversion completed AD0 conversion TIO8_udf completed TIN0S TIO8_udf DMA0 Software start TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf TIN13S Software start DMA1 CAN0_S1/S14 TID2_udf/ovf...
Page 252 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2 Common Units of Multijunction Timers The common units of MJT include the following: • Prescaler Unit • Clock Bus and Input/Output Event Bus Control Unit • Input Processing Control Unit • Output Flip-flop Control Unit •...
Page 253: Mjt Common Unit Register Map
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.1 MJT Common Unit Register Map The table below shows a common unit register map of MJT. MJT Common Unit Register Map (1/2) Address +0 address +1 address See pages b7 b8 H'0080 0200 (Use inhibited area) Clock Bus &...
Page 254 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers MJT Common Unit Register Map (2/2) Address +0 address +1 address See pages b7 b8 H'0080 07E0 PWMOFF0 Input Processing Control Register TIN24,25 Input Processing Control Register 10-171 (PWMOFF0CR) (TIN2425CR) 10-25 H'0080 07E2 TIN24,25 Interrupt Request Mask Register TIN24,25 Interrupt Request Status Register 10-53...
Page 255: Prescaler Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.2 Prescaler Unit The Prescalers PRS0–5 area an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID and TOU) from the internal peripheral clock (BCLK) divided by 2 (10 MHz when f(BCLK) = 20 MHz). The values of prescaler registers are initialized to H’00 immediately after reset.
Page 256: Clock Bus And Input/Output Event Bus Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.3 Clock Bus and Input/Output Event Bus Control Unit (1) Clock bus The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0–3. Each timer can use these clock bus signals as clock input signals.
Page 257 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer Timer Mode Timing at which signals are generated to the output event bus Single-shot output mode When the counter underflows Delayed single-shot output mode When the counter underflows...
Page 258 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TCLK0 (P124) TCLK0S TOP 6 TOP 7 TIN0 (P150) TIN0S PRS0 TOP 8 BCLK/2 PRS1 PRS2...
Page 259 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The Clock Bus and Input/Output Event Bus Control Unit has the following registers: • Clock Bus & Input Event Bus Control Register (CKIEBCR) • Output Event Bus Control Register (OEBCR) Clock Bus & Input Event Bus Control Register (CKIEBCR) <Address: H’0080 0201>...
Page 260: Input Processing Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Output Event Bus Control Register (OEBCR) <Address: H’0080 0205> OEB3S OEB2S OEB1S OEB0S <After reset: H’00> Bit Name Function 8, 9 OEB3S 00: Select TOP8 output Output event bus 3 input select bit 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output...
Page 261 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers (1) Functions of TCLK Input Processing Control Registers Item Function BCLK/2 BCLK/2 Count clock Rising edge TCLK Count clock Falling edge TCLK Count clock Both edges TCLK Count clock Low level TCLK BCLK/2 Count clock High level...
Page 262 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers (2) Functions of TIN Input Processing Control Registers Item Function Rising edge Internal edge signal Falling edge Internal edge signal Both edges Internal edge signal Low level Prescaler output period or TCLK input period Internal edge signal High level...
Page 263 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TLCK Input Processing Control Register (TCLKCR) <Address: H’0080 0210> TCLK0S TCLK3S TCLK2S TCLK1S <After reset: H’0000> Bit Name Function 0, 1 No function assigned. Fix to "0". 2, 3 TCLK3S 00: BCLK/2 TCLK3 input processing select bit 01: Rising edge 10: Falling edge...
Page 264 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN0–4 Input Processing Control Register (TIN04CR) <Address: H’0080 0212> TIN4S TIN3S TIN2S TIN1S TIN0S <After reset: H’0000> Bit Name Function No function assigned. Fix to "0". 1–3 TIN4S 000: Disable input TIN4 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges...
Page 265 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN5–8 Input Processing Control Register (TIN58CR) <Address: H’0080 0214> TIN8S TIN7S TIN6S TIN5S <After reset: H’0000> Bit Name Function No function assigned. Fix to "0". 1–3 TIN8S 000: Disable input TIN8 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges...
Page 266 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN9–11 Input Processing Control Register (TIN911CR) <Address: H’0080 0216> TIN11S TIN10S TIN9S <After reset: H’0000> Bit Name Function 0–4 No function assigned. Fix to "0". 5–7 TIN11S 000: Disable input TIN11 input processing select bit 001: Rising edge 010: Falling edge 011: Both edges...
Page 267 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN12–19 Input Processing Control Register (TIN1219CR) <Address: H’0080 0218> TIN19S TIN18S TIN17S TIN16S TIN15S TIN14S TIN13S TIN12S <After reset: H’0000> Bit Name Function 0, 1 TIN19S (TIN19 input processing select bit) 00: Disable input 2, 3 TIN18S (TIN18 input processing select bit) 01: Rising edge...
Page 268 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN24, 25 Input Processing Control Register (TIN2425CR) <Address: H’0080 07E1> TIN25S TIN24S <After reset: H’00> Bit Name Function 8–11 No function assigned. Fix to "0". 12, 13 TIN25S (TIN25 input processing select bit) 00: Disable input 14, 15 TIN24S (TIN24 input processing select bit)
Page 269: Output Flip-Flop Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.5 Output Flip-flop Control Unit The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included: • F/F6–15 Source Select Register (FF615S) • F/F16–19 Source Select Register (FF1619S) •...
Page 270 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Table 10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer Timer Mode Timing at which signals are generated to the output flip-flop Single-shot output mode When count is enabled or underflows Delayed single-shot output mode When counter underflows Continuous output mode...
Page 271 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F6–15 Source Select Register (FF615S) <Address: H’0080 0220> FS15 FS14 FS13 FS12 FS11 FS10 <After reset: H’0000> Bit Name Function 0–2 No function assigned. Fix to "0". FS15 0: TIO4 output F/F15 source select bit 1: Output event bus 0 FS14 0: TIO3 output...
Page 272 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F16–19 Source Select Register (FF1619S) <Address: H’0080 0223> FS19 FS18 FS17 FS16 <After reset: H’0000> Bit Name Function 8, 9 FS19 00: TIO8 output F/F19 source select bit 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS18...
Page 273 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F0–15 Protect Register (FF015P) <Address: H’0080 0224> FP15 FP14 FP13 FP12 FP11 FP10 <After reset: H’0000> Bit Name Function FP15 (F/F15 protect bit) 0: Enable write to F/F output bit FP14 (F/F14 protect bit) 1: Disable write to F/F output bit FP13 (F/F13 protect bit) FP12 (F/F12 protect bit)
Page 274 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F21–28 Protect Register (FF2128P) <Address: H’0080 07D5> FP21 FP22 FP23 FP24 FP25 FP26 FP27 FP28 <After reset: H’00> Bit Name Function FP21 (F/F21 protect bit) 0: Enable write to F/F output bit FP22 (F/F22 protect bit) 1: Disable write to F/F output bit FP23 (F/F23 protect bit)
Page 275 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F0–15 Data Register (FF015D) <Address: H’0080 0226> FD15 FD14 FD13 FD12 FD11 FD10 <After reset: H’0000> Bit Name Function FD15 (F/F15 output data bit) 0: F/F output data = 0 FD14 (F/F14 output data bit) 1: F/F output data = 1 FD13 (F/F13 output data bit) FD12 (F/F12 output data bit)
Page 276 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F21–28 Data Register (FF2128D) <Address: H’0080 07D7> FD21 FD22 FD23 FD24 FD25 FD26 FD27 FD28 <After reset: H’00> Bit Name Function FD21 (F/F21 output data bit) 0: F/F output data = 0 FD22 (F/F22 output data bit) 1: F/F output data = 1 FD23 (F/F23 output data bit)
Page 277 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers F/F37–44 Data Register (FF3744D) <Address: H’0080 0CD7> FD37 FD38 FD39 FD40 FD41 FD42 FD43 FD44 <After reset: H’00> Bit Name Function FD37 (F/F37 output data bit) 0: F/F output data = 0 FD38 (F/F38 output data bit) 1: F/F output data = 1 FD39 (F/F39 output data bit)
Page 278: Interrupt Control Unit
MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers 10.2.6 Interrupt Control Unit The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer: • TOP0–5 Interrupt Request Status Register (TOP05IST) •...
Page 279 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write.
Page 280 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers Example for clearing interrupt request status Interrupt request status Initial state Interrupt request Event occurs on bit 6 Event occurs on bit 4 Write to the interrupt request status Only bit 6 cleared Bit 4 data retained Program example •...
Page 281 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers The table below shows the relationship between the interrupt request signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Request Signals Generated by MJT Signal Name Generated by Interrupt Request Source (Note 1)
Page 282 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOP0–5 Interrupt Request Status Register (TOP05IST) <Address: H’0080 0230> TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0 <After reset: H’00> Bit Name Function 0, 1 No function assigned. Fix to "0". TOPIS5 (TOP5 interrupt request status bit) 0: Interrupt not requested R(Note 1) TOPIS4 (TOP4 interrupt request status bit)
Page 283 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOP05IST <H'0080 0230> TOP05IMA <H'0080 0231> TOP5udf Data bus 6-source inputs TOPIS5 TOP0-5 output interrupt request IRQ2 TOPIM5 (Level) TOP4udf TOPIS4 TOPIM4 TOP3udf TOPIS3 TOPIM3 TOP2udf TOPIS2 TOPIM2 TOP1udf TOPIS1 TOPIM1 TOP0udf TOPIS0 TOPIM0 Figure 10.2.5 Block Diagram of TOP0–5 Output Interrupt Request...
Page 284 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS) <Address: H’0080 0232> TOPIS7 TOPIS6 TOPIM7 TOPIM6 <After reset: H’00> Bit Name Function 0, 1 No function assigned. Fix to "0". TOPIS7 (TOP7 interrupt request status bit) 0: Interrupt not requested R(Note 1) TOPIS6 (TOP6 interrupt request status bit)
Page 285 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS) <Address: H’0080 0233> TOPIS9 TOPIS8 TOPIM9 TOPIM8 <After reset: H’00> Bit Name Function 0, 1 No function assigned. Fix to "0". TOPIS9 (TOP9 interrupt request status bit) 0: Interrupt not requested R(Note 1) TOPIS8 (TOP8 interrupt request status bit)
Page 286 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIO0–3 Interrupt Request Mask & Status Register (TIO03IMS) <Address: H’0080 0234> TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0 <After reset: H’00> Bit Name Function TIOIS3 (TIO3 interrupt request status bit) 0: Interrupt not requested R(Note 1) TIOIS2 (TIO2 interrupt request status bit) 1: Interrupt requested...
Page 287 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIO4–7 Interrupt Request Mask & Status Register (TIO47IMS) <Address: H’0080 0235> TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4 <After reset: H’00> Bit Name Function TIOIS7 (TIO7 interrupt request status bit) 0: Interrupt not requested R(Note 1) TIOIS6 (TIO6 interrupt request status bit) 1: Interrupt requested...
Page 288 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS) <Address: H’0080 0236> TIOIS9 TIOIS8 TIOIM9 TIOIM8 <After reset: H’00> Bit Name Function 0, 1 No function assigned. Fix to "0". TIOIS9 (TIO9 interrupt request status bit) 0: Interrupt not requested R(Note 1) TIOIS8 (TIO8 interrupt request status bit)
Page 289 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS) <Address: H’0080 0237> TMSIS1 TMSIS0 TMSIM1 TMSIM0 <After reset: H’00> Bit Name Function 8, 9 No function assigned. Fix to "0". TMSIS1 (TMS1 interrupt request status bit) 0: Interrupt not requested R(Note 1) TMSIS0 (TMS0 interrupt request status bit)
Page 290 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN0–2 Interrupt Request Mask & Status Register (TIN02IMS) <Address: H’0080 0238> TINIS2 TINIS1 TINIS0 TINIM2 TINIM1 TINIM0 <After reset: H’00> Bit Name Function No function assigned. Fix to "0". TINIS2 (TIN2 interrupt request status bit) 0: Interrupt not requested R(Note 1) TINIS1 (TIN1 interrupt request status bit)
Page 291 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN3–6 Interrupt Request Mask & Status Register (TIN36IMS) <Address: H’0080 0239> TINIS6 TINIS5 TINIS4 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3 <After reset: H’00> Bit Name Function TINIS6 (TIN6 interrupt request status bit) 0: Interrupt not requested R(Note 1) TINIS5 (TIN5 interrupt request status bit) 1: Interrupt requested...
Page 292 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN7–11 Interrupt Request Status Register (TIN711IST) <Address: H’0080 023A> TINIS11 TINIS10 TINIS9 TINIS8 TINIS7 <After reset: H’00> Bit Name Function 0–2 No function assigned. Fix to "0". TINIS11 (TIN11 interrupt request status bit) 0: Interrupt not requested R(Note 1) TINIS10 (TIN10 interrupt request status bit)
Page 293 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN711IST <H'0080 023A> TIN711IMA<H'0080 023B> TIN11edge 5-source inputs Data bus TINIS11 TIN7–11 input interrupt request IRQ8 (Level) TINIM11 TIN10edge TINIS10 TINIM4 TIN9edge TINIS9 TINIM9 TIN8edge TINIS8 TINIM8 TIN7edge TINIS7 TINIM7 Figure 10.2.14 Block Diagram of TIN7–11 Input Interrupt Request 32180 Group User’s Manual (Rev.1.0) 10-50...
Page 294 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN12–19 Interrupt Request Status Register (TIN1219IST) <Address: H’0080 023C> TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12 <After reset: H’00> Bit Name Function TINIS19 (TIN19 interrupt request status bit) 0: Interrupt not requested R(Note 1) TINIS18 (TIN18 interrupt request status bit) 1: Interrupt requested...
Page 295 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN1219IST <H'0080 023C> TIN1219IMA <H'0080 023D> TIN19edge Data bus 8-source inputs TINIS19 TIN12–19 input interrupt request IRQ10 TINIM19 (Level) TIN18edge TINIS18 TINIM18 TIN17edge TINIS17 TINIM17 TIN16edge TINIS16 TINIM16 TIN15edge TINIS15 TINIM15 TIN14edge TINIS14 TINIM14 TIN13edge...
Page 296 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN20–23 Interrupt Request Mask & Status Register (TIN2023IMS) <Address: H’0080 023E> TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 <After reset: H’00> Bit Name Function TINIS23 (TIN23 interrupt request status bit) 0: Interrupt not requested R(Note 1) TINIS22 (TIN22 interrupt request status bit) 1: Interrupt requested...
Page 297 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN26, 27 Interrupt Request Mask Register (TIN2627IMA) <Address: H’0080 0BE2> TINIM26 TINIM27 <After reset: H’00> Bit Name Function 0–5 No function assigned. Fix to "0". TINIM26 (TIN26 interrupt request mask bit) 0: Enable interrupt request TINIM27 (TIN27 interrupt request mask bit) 1: Mask (disable) interrupt request TIN26, 27 Interrupt Request Status Register (TIN2627IST)
Page 298 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN2425IST<H'0080 07E3> TIN2425IMA<H'0080 07E2> TIN2627IST<H'0080 0BE3> TIN2627IMA<H'0080 0BE2> TIN2829IST<H'0080 0CE3> TIN2829IMA<H'0080 0CE2> TIN29edge Data bus 10-source inputs TINIS29 TIN20–29 input interrupt request TINIM29 IRQ11 (Level) TIN28edge TINIS28 TINIM28 TIN27edge TINIS27 TINIM27 TIN26edge TINIS26 TINIM26 TIN25edge...
Page 299 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN2023IMS <H'0080 023E> TIN23edge Data bus TINIS23 4-source inputs To the preceding page TINIM23 TIN22edge TINIS22 TINIM22 TIN21edge TINIS21 TINIM21 TIN20edge TINIS20 TINIM20 Figure 10.2.17 Block Diagram of TIN20–29 Input Interrupt Request (2/2) 32180 Group User’s Manual (Rev.1.0) 10-56...
Page 300 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TIN30–33 Interrupt Request Mask & Status Register (TIN3033IMS) <Address: H’0080 023F> TINIS33 TINIS32 TINIS31 TINIS30 TINIM33 TINIM32 TINIM31 TINIM30 <After reset: H’00> Bit Name Function TINIS33 (TIN33 interrupt request status bit) 0: Interrupt not requested R(Note 1) TINIS32 (TIN32 interrupt request status bit) 1: Interrupt requested...
Page 301 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOU0 Interrupt Request Mask Register (TOU0IMA) <Address: H’0080 07D2> TOU0IM7 TOU0IM6 TOU0IM5 TOU0IM4 TOU0IM3 TOU0IM2 TOU0IM1 TOU0IM0 <After reset: H’00> Bit Name Function TOU0IM7 (TOU0_7 interrupt request mask bit) 0: Enable interrupt request TOU0IM6 (TOU0_6 interrupt request mask bit) 1: Mask (disable) interrupt request TOU0IM5 (TOU0_5 interrupt request mask bit)
Page 302 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOU0IMA <H'0080 07D2> TOU0IST <H'0080 07D3> TOU07udf Data bus 8-source inputs TOU0IS7 TOU0 output interrupt request 2 TOU0IM7 IRQ13 (Level) TOU06udf TOU0IS6 TOU0IM6 TOU05udf TOU0IS5 TOU0IM5 TOU04udf TOU0IS4 TOU0IM4 TOU03udf TOU0IS3 TOU0IM3 TOU02udf TOU0IS2 TOU0IM2...
Page 303 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOU1 Interrupt Request Mask Register (TOU1IMA) <Address: H’0080 0BD2> TOU1IM7 TOU1IM6 TOU1IM5 TOU1IM4 TOU1IM3 TOU1IM2 TOU1IM1 TOU1IM0 <After reset: H’00> Bit Name Function TOU1IM7 (TOU1_7 interrupt request mask bit) 0: Enable interrupt request TOU1IM6 (TOU1_6 interrupt request mask bit) 1: Mask (disable) interrupt request TOU1IM5 (TOU1_5 interrupt request mask bit)
Page 304 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOU2 Interrupt Request Mask Register (TOU2IMA) <Address: H’0080 0CD2> TOU2IM7 TOU2IM6 TOU2IM5 TOU2IM4 TOU2IM3 TOU2IM2 TOU2IM1 TOU2IM0 <After reset: H’00> Bit Name Function TOU2IM7 (TOU2_7 interrupt request mask bit) 0: Enable interrupt request TOU2IM6 (TOU2_6 interrupt request mask bit) 1: Mask (disable) interrupt request TOU2IM5 (TOU2_5 interrupt request mask bit)
Page 305 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOU1IMA <H'0080 0BD2> TOU1IST <H'0080 0BD3> TOU17udf Data bus 16-source inputs TOU1IS7 TOU1+TOU2 output interrupt request TOU1IM7 IRQ16 (Level) TOU16udf TOU1IS6 TOU1IM6 TOU15udf TOU1IS5 TOU1IM5 TOU14udf TOU1IS4 TOU1IM4 TOU13udf TOU1IS3 TOU1IM3 TOU12udf TOU1IS2 TOU1IM2 TOU11udf...
Page 306 MULTIJUNCTION TIMERS 10.2 Common Units of Multijunction Timers TOU2IMA <H'0080 0CD2> TOU2IST <H'0080 0CD3> TOU27udf Data bus TOU2IS7 To the preceding page TOU2IM7 TOU26udf TOU2IS6 TOU2IM6 TOU25udf TOU2IS5 TOU2IM5 TOU24udf TOU2IS4 TOU2IM4 TOU23udf TOU2IS3 TOU2IM3 TOU22udf TOU2IS2 TOU2IM2 TOU21udf TOU2IS1 TOU2IM1 TOU20udf TOU2IS0...
Page 307: Top (Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3 TOP (Output-Related 16-Bit Timer) 10.3.1 Outline of TOP TOP (Timer OutPut) is an output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software: • Single-shot output mode •...
Page 308 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TOP 0 Reload register IRQ2 Down-counter F/F0 TO 0 (P110) Correction register (16-bit) IRQ2 TCLK0 (P124) TCLK0S...
Page 309: Outline Of Each Mode Of Top
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.2 Outline of Each Mode of TOP Each mode of TOP is outlined below. For each TOP channel, only one of the following modes can be selected. (1) Single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops.
Page 310 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) <Count clock-dependent delay> • Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted.
Page 311: Top Related Register Map
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.3 TOP Related Register Map Shown below is a TOP related register map. TOP Related Register Map (1/2) Address +0 address +1 address See pages b7 b8 H'0080 0240 TOP0 Counter 10-75 (TOP0CT) H'0080 0242 TOP0 Reload Register 10-76...
Page 312 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) TOP Related Register Map (2/2) Address +0 address +1 address See pages b7 b8 H'0080 029A TOP0–5 Control Register 0 10-71 (TOP05CR0) H'0080 029C (Use inhibited area) TOP0–5 Control Register 1 10-71 (TOP05CR1) (Use inhibited area) H'0080 02A0 TOP6 Counter...
Page 313: Top Control Registers
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.4 TOP Control Registers The TOP control registers are used to select operation modes of TOP0–10 (single-shot output, delayed single- shot output or continuous output mode), as well as select the count enable and count clock sources. Following four TOP control registers are provided for each timer group.
Page 314 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) TOP0–5 Control Register 0 (TOP05CR0) <Address: H’0080 029A> TOP3M TOP2M TOP1M TOP0M TOP05ENS TOP05CKS <After reset: H’0000> Bit Name Function 0, 1 TOP3M (TOP3 operation mode select bit) 00: Single-shot output mode 2, 3 TOP2M (TOP2 operation mode select bit) 01: Delayed single-shot output mode 4, 5...
Page 315 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TIN0 (P150) TIN0S S : Selector Note: • This diagram only illustrates TOP control registers and is partly omitted. Figure 10.3.3 Outline Diagram of TOP0–5 Clock and Enable Inputs 32180 Group User’s Manual (Rev.1.0) 10-72...
Page 316 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) TOP6,7 Control Register (TOP67CR) <Address: H’0080 02AA> TOP7 TOP7M TOP6M TOP67ENS TOP67CKS <After reset: H’0000> Bit Name Function No function assigned. Fix to "0". TOP7ENS 0: Result selected by TOP67ENS bit TOP7 enable source select bit 1: TOP6 output 2, 3 TOP7M...
Page 317 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) TOP8–10 Control Register (TOP810CR) <Address: H’0080 02EA> TOP810 TOP10M TOP9M TOP8M TOP810CKS <After reset: H’0000> Bit Name Function 0, 1 No function assigned. Fix to "0". 2, 3 TOP10M (TOP10 operation mode select bit) 00: Single-shot output mode 4, 5 TOP9M (TOP9 operation mode select bit)
Page 318: Top Counters (Top0Ct-Top10Ct)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.5 TOP Counters (TOP0CT–TOP10CT) TOP0 Counter (TOP0CT) <Address: H’0080 0240> TOP1 Counter (TOP1CT) <Address: H’0080 0250> TOP2 Counter (TOP2CT) <Address: H’0080 0260> TOP3 Counter (TOP3CT) <Address: H’0080 0270> TOP4 Counter (TOP4CT) <Address: H’0080 0280> TOP5 Counter (TOP5CT) <Address: H’0080 0290>...
Page 319: Top Reload Registers (Top0Rl-Top10Rl)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.6 TOP Reload Registers (TOP0RL–TOP10RL) TOP0 Reload Register (TOP0RL) <Address: H’0080 0242> TOP1 Reload Register (TOP1RL) <Address: H’0080 0252> TOP2 Reload Register (TOP2RL) <Address: H’0080 0262> TOP3 Reload Register (TOP3RL) <Address: H’0080 0272> TOP4 Reload Register (TOP4RL) <Address: H’0080 0282>...
Page 320: Top Correction Registers (Top0Cc-Top10Cc)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.7 TOP Correction Registers (TOP0CC–TOP10CC) TOP0 Correction Register (TOP0CC) <Address: H’0080 0246> TOP1 Correction Register (TOP1CC) <Address: H’0080 0256> TOP2 Correction Register (TOP2CC) <Address: H’0080 0266> TOP3 Correction Register (TOP3CC) <Address: H’0080 0276> TOP4 Correction Register (TOP4CC) <Address: H’0080 0286>...
Page 321: Top Enable Control Registers
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.8 TOP Enable Control Registers TOP External Enable Permit Register (TOPEEN) <Address: H’0080 02FA> TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 <After reset: H’0000> Bit Name Function 0–4 No function assigned. Fix to "0". TOP10EEN (TOP10 external enable permit bit) 0: Disable external enable TOP9EEN (TOP9 external enable permit bit)
Page 322 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) TOP Count Enable Register (TOPCEN) <Address: H’0080 02FE> TOP10 TOP9 TOP8 TOP7 TOP6 TOP5 TOP4 TOP3 TOP2 TOP1 TOP0 <After reset: H’0000> Bit Name Function 0–4 No function assigned. Fix to "0". TOP10CEN (TOP10 count enable bit) 0: Stop counting TOP9CEN (TOP9 count enable bit) 1: Enable counting...
Page 323: Operation In Top Single-Shot Output Mode (With Correction Function)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) (1) Outline of TOP single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops.
Page 324 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the reload register is initially set to H’A000. (The initial counter value can be undefined, and does not have to be specific.) When the timer starts, the reload register value is loaded into the counter, letting it start counting.
Page 325 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (2) Correction function of TOP single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is.
Page 326 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the reload register is initially set to H’8000. When the timer starts, the reload register value is loaded into the counter, letting it start counting down. In the diagram below, the value H’4000 is written to the correction register when the counter has counted down to H’5000.
Page 327 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (3) Precautions on using TOP single-shot output mode The following describes precautions to be observed when using TOP single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
Page 328 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the reload register is initially set to H’FFF8. When the timer starts, the reload register value is loaded into the counter, letting it start counting down. In the diagram below, the value H’0014 is written to the correction register when the counter has counted down to H’FFF0.
Page 329: Operation In Top Delayed Single-Shot Output Mode (With Correction Function)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) (1) Outline of TOP delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops.
Page 330 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down.
Page 331 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (2) Correction function of TOP delayed single-shot output mode To change the counter value while in progress, write to the TOP correction register a value by which the counter value is to be increased or reduced from its initial set value. To add, write the value to be added to the correction register directly as is.
Page 332 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the counter and the reload register are initially set to H’A000 and H’F000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down.
Page 333 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (3) Precautions on using TOP delayed single-shot output mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
Page 334: Operation In Top Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) (1) Outline of TOP continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value.
Page 335 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) In the example below, the counter and the reload register are initially set to H’A000 and H’E000, respectively. When the timer is enabled, the counter starts counting down and when it underflows after reaching the minimum count, the counter is loaded with the content of the reload register and continues counting down.
Page 336 MULTIJUNCTION TIMERS 10.3 TOP (Output-Related 16-Bit Timer) (2) Precautions on using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
Page 337: Tio (Input/Output-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.1 Outline of TIO TIO (Timer Input/Output) is an input/output-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: <Input modes>...
Page 338 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TIO 0 Reload 0/measure register IRQ0 F/F11 TO 11 (P103) Down-counter Reload 1 register (Note 1) IRQ12 (16-bit) en/cap...
Page 339: Outline Of Each Mode Of Tio
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.2 Outline of Each Mode of TIO Each mode of TIO is outlined below. For each TIO channel, only one of the following modes can be selected. (1) Measure clear/free-run input modes In measure clear/free-run input modes, the timer is used to measure a duration of time from when the counter starts counting till when an external capture signal is entered.
Page 340 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and then stops. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload 0 register, the counter is loaded with the reload 0 register value and starts counting synchronously with the count clock.
Page 341 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) <Count clock-dependent delay> • Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is inverted.
Page 342: Tio Related Register Map
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.3 TIO Related Register Map Shown below is a TIO related register map. TIO Related Register Map (1/2) Address +0 address +1 address See pages b7 b8 H'0080 0300 TIO0 Counter 10-109 (TIO0CT) H'0080 0302 (Use inhibited area) H'0080 0304...
Page 343 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO Related Register Map (2/2) Address +0 address +1 address See pages b7 b8 H'0080 0350 TIO5 Counter 10-109 (TIO5CT) H'0080 0352 (Use inhibited area) H'0080 0354 TIO5 Reload 1 Register 10-111 (TIO5RL1) H'0080 0356 TIO5 Reload 0/Measure Register 10-110...
Page 344: Tio Control Registers
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.4 TIO Control Registers The TIO control registers are used to select operation modes of TIO0–9 (measure input, noise processing input, PWM output, single-shot output, delayed single-shot output or continuous output mode), as well as select the count enable and count clock sources.
Page 345 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO0–3 Control Register 0 (TIO03CR0) <Address: H’0080 031A> TIO3EEN TIO3M TIO2ENS TIO2M TIO1ENS TIO1M TIO0ENS TIO0M <After reset: H’0000> Bit Name Function TIO3EEN (Note 1) 0: Disable external input TIO3 external input enable bit 1: Enable external input 1–3 TIO3M...
Page 346 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 TIO 0 en/cap TIN3 (P153) TIN3S TIO 1 en/cap TIN4 (P154) TIN4S TIO 2 en/cap TIN5 (P155) TIN5S TIO 3 en/cap TIO 4 en/cap...
Page 347 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO4 Control Register (TIO4CR) <Address: H’0080 034A> TIO4CKS TIO4EEN TIO34ENS TIO4M <After reset: H’0000> Bit Name Function 0, 1 TIO4CKS 00: Clock bus 3 TIO4 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3 TIO4EEN (Note 1)
Page 348 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Clock bus Input event bus 3 2 1 0 3 2 1 0 TCLK1S TCLK1 (P125) TIO 5 en/cap TIN7 (P157) TIN7S TCLK2 (P126) TCLK2S TIO 6 en/cap TIN8 (P140) TIN8S TIO 7 en/cap TIN9 (P141) TIN9S...
Page 349 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO5 Control Register (TIO5CR) <Address: H’0080 034B> TIO5CKS TIO5ENS TIO5M <After reset: H’00> Bit Name Function 8–10 TIO5CKS 000: External input TCLK1 TIO5 clock source select bit 001: – ditto – 010: – ditto – 011: –...
Page 350 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO6 Control Register (TIO6CR) <Address: H’0080 036A> TIO6CKS TIO6ENS TIO6M <After reset: H’00> Bit Name Function 0–2 TIO6CKS 000: External input TCLK2 TIO6 clock source select bit 001: – ditto – 010: – ditto – 011: –...
Page 351 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO7 Control Register (TIO7CR) <Address: H’0080 036B> TIO7CKS TIO7ENS TIO7M <After reset: H’00> Bit Name Function No function assigned. Fix to "0". 9, 10 TIO7CKS 00: Clock bus 0 TIO7 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3...
Page 352: Tio Counters (Tio0Ct-Tio9Ct)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO9 Control Register (TIO9CR) <Address: H’0080 038B> TIO9CKS TIO9ENS TIO9M <After reset: H’00> Bit Name Function No function assigned. Fix to "0". 9, 10 TIO9CKS 00: Clock bus 0 TIO9 clock source select bit 01: Clock bus 1 10: Clock bus 2 11: Clock bus 3...
Page 353: Tio Reload 0/ Measure Registers (Tio0Rl0-Tio9Rl0)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0–TIO9RL0) TIO0 Reload 0/ Measure Register (TIO0RL0) <Address: H’0080 0306> TIO1 Reload 0/ Measure Register (TIO1RL0) <Address: H’0080 0316> TIO2 Reload 0/ Measure Register (TIO2RL0) <Address: H’0080 0326> TIO3 Reload 0/ Measure Register (TIO3RL0) <Address: H’0080 0336>...
Page 354: Tio Reload 1 Registers (Tio0Rl1-Tio9Rl1)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.7 TIO Reload 1 Registers (TIO0RL1–TIO9RL1) TIO0 Reload 1 Register (TIO0RL1) <Address: H’0080 0304> TIO1 Reload 1 Register (TIO1RL1) <Address: H’0080 0314> TIO2 Reload 1 Register (TIO2RL1) <Address: H’0080 0324> TIO3 Reload 1 Register (TIO3RL1) <Address: H’0080 0334>...
Page 355: Tio Enable Control Registers
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.8 TIO Enable Control Registers TIO Enable Protect Register (TIOPRO) <Address: H’0080 03BC> TIO9PRO TIO8PRO TIO7PRO TIO6PRO TIO5PRO TIO4PRO TIO3PRO TIO2PRO TIO1PRO TIO0PRO <After reset: H’0000> Bit Name Function 0–5 No function assigned. Fix to "0". TIO9PRO (TIO9 enable protect bit) 0: Enable rewrite TIO8PRO (TIO8 enable protect bit)
Page 356 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) TIO Count Enable Register (TIOCEN) <Address: H’0080 03BE> TIO9CEN TIO8CEN TIO7CEN TIO6CEN TIO5CEN TIO4CEN TIO3CEN TIO2CEN TIO1CEN TIO0CEN <After reset: H’0000> Bit Name Function 0–5 No function assigned. Fix to "0". TIO9CEN (TIO9 count enable bit) 0: Stop count TIO8CEN (TIO8 count enable bit) 1: Enable count...
Page 357: Operation In Tio Measure Free-Run/ Clear Input Modes
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes (1) Outline of TIO measure free-run/ clear input modes In measure free-run/ clear input modes, the timer is used to measure a duration of time from when the counter starts counting till when an external capture signal is entered.
Page 358 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Enabled Measure event (by writing to the enable bit) (capture) occurs Count clock Enable bit H'FFFF Undefined value Counter H'7000 H'0000 Measure register Undefined H'0008 TIN interrupt request TIN interrupt request due to external event input TIO interrupt request TIO interrupt request due...
Page 359: Operation In Tio Noise Processing Input Mode
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.10 Operation in TIO Noise Processing Input Mode In noise processing input mode, the timer is used to detect that the input signal remained in the same state for over a predetermined time. In noise processing input mode, a high or low level on external input activates the counter and if the input signal remains in the same state for over a predetermined time before the counter underflows, the counter generates an interrupt request before stopping.
Page 360: Operation In Tio Pwm Output Mode
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.11 Operation in TIO PWM Output Mode (1) Outline of TIO PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled (by writing to the enable bit in software or by external input) after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock.
Page 361 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) (2) Reload register updates in TIO PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated by updating the reload 0 register.
Page 362 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 (Reload 1 data latched) Write to reload 1 H'1000 H'8000 Reload 0 register Reload 1 register H'2000 H'9000...
Page 363: Operation In Tio Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) (1) Outline of TIO single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once and then stops.
Page 364 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Enabled (by writing to the enable bit Disabled (by underflow) or by external input) Count clock Enable bit H'FFFF Undefined value Count down from the reload 0 register set value H'A000 H'(A000-1) Counter H'0000 H'A000 Reload 0 register...
Page 365: Operation In Tio Delayed Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TIO delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops.
Page 366 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Enabled (by writing to the enable bit Underflow Underflow or by external input) (first time) (second time) Count clock Enable bit H'FFFF H'F000 H'EFFF Count down from the Count down from the reload 0 register counter set value H'A000 set value...
Page 367: Operation In Tio Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) (1) Outline of TIO continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload 0 register value.
Page 368 MULTIJUNCTION TIMERS 10.4 TIO (Input/Output-Related 16-Bit Timer) Enabled (by writing to the enable bit Underflow Underflow or by external input) (second time) (first time) Count clock Enable bit H'FFFF H'DFFF H'DFFF H'E000 Count down from the Count down from the Count down from reload 0 register reload 0 register...
Page 369: Tms (Input-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) 10.5 TMS (Input-Related 16-Bit Timer) 10.5.1 Outline of TMS TMS (Timer Measure Small) is an input-related 16-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TMS.
Page 370 MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) Clock bus Input event bus Output event bus 3 2 1 0 3 2 1 0 0 1 2 3 TMS 0 IRQ7 TCLK3 (P127) TCLK3S Measure register 3 Counter (16-bit) Measure register 2 Measure register 1 Measure register 0 cap3...
Page 371: Tms Related Register Map
MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) <Count clock-dependent delay> • Because the timer operates synchronously with the count clock, there is a count clock-dependent delay from when the timer is enabled till when it actually starts operating. Write to the enable bit BCLK Count clock period Count clock...
Page 372: Tms Control Registers
MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) 10.5.4 TMS Control Registers The TMS control registers are used to select TMS0/1 input events and count clock sources, as well as control count enable. Following two TMS control registers are included: • TMS0 Control Register (TMS0CR) •...
Page 373: Tms Counters (Tms0Ct, Tms1Ct)
MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) 10.5.5 TMS Counters (TMS0CT, TMS1CT) TMS0 Counter (TMS0CT) <Address: H’0080 03C0> TMS1 Counter (TMS1CT) <Address: H’0080 03D0> TMS0CT,TMS1CT <After reset: Undefined> Bit Name Function 0–15 TMS0CT, TMS1CT 16-bit counter value Note: • This register must always be accessed in halfwords. The TMS counters are a 16-bit up-counter, which starts counting when the timer is enabled (by writing to the enable bit in software).
Page 374: Operation Of Tms Measure Input
MULTIJUNCTION TIMERS 10.5 TMS (Input-Related 16-Bit Timer) 10.5.7 Operation of TMS Measure Input (1) Outline of TMS measure input In TMS measure input, when the timer is enabled (by writing to the enable bit in software), it starts counting up synchronously with the count clock. Then when event input to TMS is detected while the timer is operat- ing, the counter value is latched into measure registers 0–3.
Page 375: Tml (Input-Related 32-Bit Timer)
MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) 10.6 TML (Input-Related 32-Bit Timer) 10.6.1 Outline of TML TML (Timer Measure Large) is an input-related 32-bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels. The table below shows specifications of TML.
Page 376: Outline Of Tml Operation
MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) 10.6.2 Outline of TML Operation In TML, the timer starts counting upon deassertion of the reset input signal. The counter included in the timer is a 32-bit up-counter, where when a measure event signal is entered from an external device, the counter value at that point in time is stored in each 32-bit measure register.
Page 377: Tml Control Registers
MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) 10.6.4 TML Control Registers TML0 Control Register (TML0CR) <Address: H’0080 03EB> TML0SS0 TML0SS1 TML0SS2 TML0SS3 TML0CKS <After reset: H’00> Bit Name Function TML0SS0 0: External input TIN23 TML0 measure 0 source select bit 1: Input event bus 0 TML0SS1 0: External input TIN22...
Page 378: Tml Counters
MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) 10.6.5 TML Counters TML0 Counter (TML0CT) <Address: H’0080 03E0> TML1 Counter (TML1CT) <Address: H’0080 0FE0> TML0CT, TML1CT(16 high-order bits) (16 low-order bits) <After reset: Undefined> Bit Name Function 0–31 TML0CT 32-bit counter value R(Note 1) Note 1: If the clock source selected for the counter is not BCLK/2, do not write to this register.
Page 379: Operation Of Tml Measure Input
MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) 10.6.7 Operation of TML Measure Input (1) Outline of TML measure input In TML measure input, when the reset input signal is deasserted, the counter starts counting up synchro- nously with the count clock. Upon event input to measure registers 0–3, the counter value is latched into each measure register.
Page 380 MULTIJUNCTION TIMERS 10.6 TML (Input-Related 32-Bit Timer) (2) Precautions on using TML measure input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched into the measure register.
Page 381: Tid (Input-Related 16-Bit Timer)
MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 10.7 TID (Input-Related 16-Bit Timer) 10.7.1 Outline of TID TID (Timer Input Derivation) is an input-related 16-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time: •...
Page 382 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) Output event bus 0 TID 0 Reload register BCLK/2 Clock PRS3 IRQ14 Up/down-counter control DMA0 TIN24S IRQ11 CLK1 CLK2 TIN24(P172) TIN25(P173) IRQ11 TOU0_0–7en TOU0_7udf TIN25S TID 1 Reload register IRQ15, BCLK/2 Clock PRS4 AD1TRG(To A-D1 converter) Up/down-counter control...
Page 383: Tid Related Register Map
MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 10.7.2 TID Related Register Map Shown below is a TID related register map. TID Related Register Map Address +0 address +1 address See pages b7 b8 H'0080 078C TID0 Counter 10-144 (TID0CT) H'0080 078E TID0 Reload Register 10-144 (TID0RL)
Page 384: Tid Control & Prescaler Enable Registers
MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 10.7.3 TID Control & Prescaler Enable Registers TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) <Address: H’0080 07D1> TID0M TID0CEN TOU0ENS PRS3EN <After reset: H’00> Bit Name Function 8–10 TID0M 000: Fixed period count mode TID0 operation mode select bit 001: –...
Page 385 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) <Address: H’0080 0BD1> TID1M TID1CEN TOU1ENO PRS4EN <After reset: H’00> Bit Name Function 8–10 TID1M 000: Fixed period count mode TID1 operation mode select bit 001: –...
Page 386 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) <Address: H’0080 0CD1> TID2M TID2CEN TOU2ENO PRS5EN <After reset: H’00> Bit Name Function 8–10 TID2M 000: Fixed period count mode TID2 operation mode select bit 001: –...
Page 387: Tid Counters (Tid0Ct, Tid1Ct And Tid2Ct)
MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 10.7.4 TID Counters (TID0CT, TID1CT and TID2CT) TID0 Counter (TID0CT) <Address: H’0080 078C> TID1 Counter (TID1CT) <Address: H’0080 0B8C> TID2 Counter (TID2CT) <Address: H’0080 0C8C> TID0CT, TID1CT, TID2CT <After reset: Undefined> Bit Name Function 0–15 TID0CT, TID1CT, TID2CT...
Page 388: Outline Of Each Mode Of Tid
MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) 10.7.6 Outline of Each Mode of TID Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time. (1) Fixed period count mode In fixed period count mode, the timer uses a reload register to generate an interrupt request at intervals of (reload register set value + 1).
Page 389 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) (2) Event count mode In event count mode, the timer uses an external input signal (TIN24, TIN26 or TIN28) as the clock source for the counter. Note: • TIN25, TIN27 and TIN29 cannot be used as the clock source for the counter. By detecting the rising and falling edges of the external input signal (TIN24, TIN26 or TIN28), the timer generates clock pulses synchronized to the microcomputer’s internal clock.
Page 390 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) (3) Multiply-by-4 event count mode In multiply-by-4 event count mode, the timer uses two external input signals in pairs (TIN24 and TIN25, TIN26 and TIN27, or TIN28 and TIN29) as the clock sources for the counter. The count direction is switched between up-count and down-count depending on the status of the two input signals.
Page 391 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) TIN24 (TIN26, TIN28) TIN25 (TIN27, TIN29) Counter value 7FFE 7FFF 8000 8001 8002 8003 8002 8001 8000 7FFF 7FFE Switched over 8003 Counter 7FFE Down-count Up-count Figure 10.7.6 Multiply-by-4 Count Operation (Switchover Timing) TIN24 (TIN26, TIN28) TIN25...
Page 392 MULTIJUNCTION TIMERS 10.7 TID (Input-Related 16-Bit Timer) (4) Up/down event count mode In up/down event count mode, the timer uses one of two-channel external input signals (TIN24, TIN26 or TIN28) as the clock source for the counter and the other (TIN25, TIN27 or TIN29) as an up/down select signal.
Page 393: Tou (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8 TOU (Output-Related 24-Bit Timer) 10.8.1 Outline of TOU TOU (Timer Output Unification) is an output-related 24-bit timer, whose operation mode can be selected from the following by mode switching in software, one at a time. <Output modes without correction function>...
Page 394 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Output event bus TIN16/PWMOFF0 PWMOFF0S PO0DIS IRQ13 (P130) TOU0_0 (24-bit) F/F21 TO21 (P160) DMA5 IRQ13 TOU0_1 (24-bit) F/F22 TO22 (P161) DMA6 IRQ13 F/F23 TOU0_2 (24-bit) TO23 (P162) DMA7 IRQ13 TOU0_3 (24-bit) F/F24 TO24 (P163) IRQ13 TOU0_4 (24-bit) F/F25...
Page 395: Outline Of Each Mode Of Tou
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.2 Outline of Each Mode of TOU Each mode of TOU is outlined below. Modes on each TOU channel can be selected from the following, only one at a time. (1) PWM output mode (without correction function) In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle.
Page 396 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (4) Single-shot output mode (without correction function) In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the content of the reload register and starts counting synchronously with the count clock.
Page 397: Tou Related Register Map
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.3 TOU Related Register Map Shown below is a TOU related register map. TOU Related Register Map (1/4) Address +0 address +1 address See pages b7 b8 H'0080 0780 PWM Output 0 Disable Control Register PWM Output 0 Disable Level Control Register 10-174 (PO0DISCR)
Page 398 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU Related Register Map (2/4) Address +0 address +1 address See pages b7 b8 H'0080 07C8 TOU0_7 Counter (Upper) 10-161 (TOU07CTW) (TOU07CTH) H'0080 07CA (Lower) 10-163 (TOU07CT) H'0080 07CC TOU0_7 Reload Register TOU0_7 Reload 1 Register 10-164 (TOU07RLW) (TOU07RL1)
Page 399 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU Related Register Map (3/4) Address +0 address +1 address See pages b7 b8 H'0080 0BB8 TOU1_5 Counter (Upper) 10-161 (TOU15CTW) (TOU15CTH) H'0080 0BBA (Lower) 10-163 (TOU15CT) H'0080 0BBC TOU1_5 Reload Register TOU1_5 Reload 1 Register 10-164 (TOU15RLW) (TOU15RL1)
Page 400 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU Related Register Map (4/4) Address +0 address +1 address See pages b7 b8 H'0080 0CA8 TOU2_3 Counter (Upper) 10-161 (TOU23CTW) (TOU23CTH) H'0080 0CAA (Lower) 10-163 (TOU23CT) H'0080 0CAC TOU2_3 Reload Register TOU2_3 Reload 1 Register 10-164 (TOU23RLW) (TOU23RL1)
Page 401: Tou Control Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.4 TOU Control Registers TOU0 Control Register 0 (TOU0CR0) <Address: H’0080 07DA> TOU00M0 TOU01M0 TOU02M0 TOU03M0 TOU04M0 TOU05M0 TOU06M0 TOU07M0 <After reset: H’0000> Bit Name Function 0, 1 TOU00M0 (TOU0_0 operation mode select 0 bit) 00: Single-shot output mode 2, 3 TOU01M0 (TOU0_1 operation mode select 0 bit)
Page 402 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU1 Control Register 0 (TOU1CR0) <Address: H’0080 0BDA> TOU10M0 TOU11M0 TOU12M0 TOU13M0 TOU14M0 TOU15M0 TOU16M0 TOU17M0 <After reset: H’0000> Bit Name Function 0, 1 TOU10M0 (TOU1_0 operation mode select 0 bit) 00: Single-shot output mode 2, 3 TOU11M0 (TOU1_1 operation mode select 0 bit) 01: Single-shot PWM output mode...
Page 403 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU2 Control Register 0 (TOU2CR0) <Address: H’0080 0CDA> TOU20M0 TOU21M0 TOU22M0 TOU23M0 TOU24M0 TOU25M0 TOU26M0 TOU27M0 <After reset: H’0000> Bit Name Function 0, 1 TOU20M0 (TOU2_0 operation mode select 0 bit) 00: Single-shot output mode 2, 3 TOU21M0 (TOU2_1 operation mode select 0 bit) 01: Single-shot PWM output mode...
Page 404: Tou Counters
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.5 TOU Counters The TOU counters are functionally different depending on the timer’s operation mode. (1) TOU counters during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Counter (TOU00CTW) <Address: H’0080 0790> TOU0_1 Counter (TOU01CTW) <Address: H’0080 0798>...
Page 405 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) The TOU counters operate as a 24-bit down-counter when in single-shot output, delayed single-shot output or continuous output mode. After the timer is enabled (by writing to the enable bit in software or upon occurrence of the event selected by the TOU enable source select bit), the counter starts counting synchronously with the count clock.
Page 406 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (2) TOU counters during PWM output and single-shot PWM output modes TOU0_0 Counter (TOU00CT) <Address: H’0080 0792> TOU0_1 Counter (TOU01CT) <Address: H’0080 079A> TOU0_2 Counter (TOU02CT) <Address: H’0080 07A2> TOU0_3 Counter (TOU03CT) <Address: H’0080 07AA> TOU0_4 Counter (TOU04CT) <Address: H’0080 07B2>...
Page 407: Tou Reload Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.6 TOU Reload Registers The TOU reload registers are used to load data into the TOU counters. These registers are functionally different depending on the timer’s operation mode. (1) TOU reload registers during single-shot output, delayed single-shot output and continuous output modes TOU0_0 Reload Register (TOU00RLW) <Address: H'0080 0794>...
Page 408 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) During single-shot output, delayed single-shot output and continuous output modes, TOU operates as a 24-bit timer. The value set in the 24 low-order bits of the reload register is loaded into the counter. Bits 8–15 and bits 16–31 are the 8 high-order and the 16 low-order bits of the counter, respectively.
Page 409 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (2) TOU reload registers during PWM output and single-shot PWM output modes TOU0_0 Reload 0 Register (TOU00RL0) <Address: H'0080 0796> TOU0_1 Reload 0 Register (TOU01RL0) <Address: H'0080 079E> TOU0_2 Reload 0 Register (TOU02RL0) <Address: H'0080 07A6>...
Page 410 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU0_0 Reload 1 Register (TOU00RL1) <Address: H'0080 0794> TOU0_1 Reload 1 Register (TOU01RL1) <Address: H'0080 079C> TOU0_2 Reload 1 Register (TOU02RL1) <Address: H'0080 07A4> TOU0_3 Reload 1 Register (TOU03RL1) <Address: H'0080 07AC> TOU0_4 Reload 1 Register (TOU04RL1) <Address: H'0080 07B4>...
Page 411: Tou Enable Protect Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.7 TOU Enable Protect Registers TOU0 Enable Protect Register (TOU0PRO) <Address: H'0080 07DD> TOU1 Enable Protect Register (TOU1PRO) <Address: H'0080 0BDD> TOU2 Enable Protect Register (TOU2PRO) <Address: H'0080 0CDD> TOUn TOUn TOUn TOUn TOUn TOUn TOUn...
Page 412: Tou Count Enable Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.8 TOU Count Enable Registers TOU0 Count Enable Register (TOU0CEN) <Address: H’0080 07DF> TOU1 Count Enable Register (TOU1CEN) <Address: H'0080 0BDF> TOU2 Count Enable Register (TOU2CEN) <Address: H'0080 0CDF> TOUn TOUn TOUn TOUn TOUn TOUn TOUn...
Page 413 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) TOU0 enable source selection (TOU0ENS) Event enable disable TID0_udf/ovf EN-ON TOU0_7udf Output event bus 0 TIN25S TOU0m enable (TOU0mCEN) TOU0m enable control TOU0m enable protect (TOU0mPRO) Figure 10.8.4 Configuration of the TOU0 Enable Circuit TOU1 enable source selection (TOU1ENS) Event enable...
Page 414: Pwmoff Input Processing Control Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.9 PWMOFF Input Processing Control Registers PWMOFF0 Input Processing Control Register (PWMOFF0CR) <Address: H'0080 07E0> PWMOFF0S OFF0SP <After reset: H’00> Bit Name Function 0–3 No function assigned. Fix to "0". PWMOFF0SP PWMOFF0S write control bit 5–7 PWMOFF0S 000: Input has no effect...
Page 415 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) PWMOFF2 Input Processing Control Register (PWMOFF2CR) <Address: H'0080 0CE0> PWMOFF2S OFF2SP <After reset: H’00> Bit Name Function 0–3 No function assigned. Fix to "0". PWMOFF2SP PWMOFF2S write control bit 5–7 PWMOFF2S 000: Input has no effect PWMOFF2 input processing control bit 001: Rising edge 010: Falling edge...
Page 416 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) • Example of correct settings PWMOFFnSP "1" If a write cycle to any other area occurs during this interval, the value that was set in the PWMOFFnS bits is not reflected. PWMOFFnSP "0" PWMOFFnS Set value •...
Page 417: Pwm Output Control Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.10 PWM Output Control Registers PWM Output 0 Disable Control Register (PO0DISCR) <Address: H’0080 0780> PO0DISP PO0DIS <After reset: H’00> Bit Name Function 0–5 No function assigned. Fix to "0". PO0DISP – PO0DIS write control bit PO0DIS 0: Enable output P160/TO21–P165/TO26 output disable select bit...
Page 418 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) PWM Output 2 Disable Control Register (PO2DISCR) <Address: H'0080 0784> PO2DISP PO2DIS <After reset: H’00> Bit Name Function 0–5 No function assigned. Fix to "0". PO2DISP – PO2DIS write control bit PO2DIS 0: Enable output P210/TO37–P215/TO42 output disable select bit 1: Disable output These registers control output from the respective corresponding pins by enabling or disabling it.
Page 419 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) • Example of correct settings POnDISP "1" If a write cycle to any other area occurs during this interval, the value that was set in the POnDIS bit is not reflected. POnDISP "0" POnDIS Set value •...
Page 420: Pwm Output Disable Level Control Registers
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.11 PWM Output Disable Level Control Registers PWM Output 0 Disable Level Control Register (PO0LVCR) <Address: H'0080 0781> PO0LVSEL PO0LVEN <After reset: H’00> Bit Name Function 8–13 No function assigned. Fix to "0". PO0LVSEL 0: Select low output disable level P160/TO21–P165/TO26 output disable level select bit 1: Select high output disable level...
Page 421 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (1) POnLVSEL (Output Disable Level Select) bit (Bit 14) This bit specifies the level (high or low) at which port output is to be disabled. Set this bit to "0" to disable port output when its level is low, or "1"...
Page 422: Operation In Tou Pwm Output Mode
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.12 Operation in TOU PWM Output Mode (1) Outline of TOU PWM output mode In PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle. When the timer is enabled after setting the initial values in the reload 0 and reload 1 registers, the counter is loaded with the reload 0 register value and starts counting down synchronously with the count clock.
Page 423 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Enabled Underflow Underflow (by writing to the enable bit (first time) (second time) or by external input) Count clock Enable bit Count down from the Count down from the Count down from the reload 0 register reload 0 register reload 1 register...
Page 424 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (2) Reload register updates in TOU PWM output mode In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the same time data are written to the respective registers. But when the timer is operating, the reload 1 register is updated by updating the reload 0 register.
Page 425 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 Write to reload 1 (Reload 1 data latched) Reload 0 register H'1000 H'8000 Reload 1 register H'2000 H'9000...
Page 426 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (a) When reload register updates take effect in the current period (reflected in the next period) Write to reload 0 (Reload 1 data latched) Write to reload 1 Reload 0 register H'1000 FFFF Reload 1 register H'2000 H'9000...
Page 427: Operation In Tou Single-Shot Pwm Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.13 Operation in TOU Single-shot PWM Output Mode (without Correction Function) (1) Outline of TOU single-shot PWM output mode In single-shot PWM output mode, the timer uses two reload registers to generate a waveform with a given duty cycle only once.
Page 428 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Enabled Underflow Underflow (by writing to the enable bit (first time) (second time) or by external input) Count clock Enable bit H'FFFF H'F000 H'EFFF Undefined Count down from the Count down from the value reload 0 register reload 1 register...
Page 429: Operation In Tou Delayed Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.14 Operation in TOU Delayed Single-shot Output Mode (without Correction Function) (1) Outline of TOU delayed single-shot output mode In delayed single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) after a finite time equal to (counter set value + 1) only once and then stops.
Page 430 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Enabled Underflow Underflow (by writing to the enable bit (first time) (second time) or by external input) Count clock Enable bit H'FF FFFF H'10 F000 Undefined H'10 EFFF value Count down from the Count down from the counter set value reload register...
Page 431: Operation In Tou Single-Shot Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.15 Operation in TOU Single-shot Output Mode (without Correction Function) (1) Outline of TOU single-shot output mode In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once and then stops.
Page 432 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Enabled (by writing to the enable bit Disable or by external input) (due to underflow) Count clock Enable bit H'FF FFFF Undefined Count down from the value reload 0 register set value H'55 AA00 H'(55 AA00-1) Counter H'00 0000...
Page 433: Operation In Tou Continuous Output Mode (Without Correction Function)
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.16 Operation in TOU Continuous Output Mode (without Correction Function) (1) Outline of TOU continuous output mode In continuous output mode, the timer counts down starting from the set value of the counter and when the counter underflows, it is loaded with the reload register value.
Page 434 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Enabled (by writing to the enable bit Underflow Underflow or by external input) (first time) (second time) Count clock Enable bit H'FF FFFF H'00 FFFF H'0D FFFF Undefined H'0E 0000 value Count down from the Count down from the Count down from the counter set value...
Page 435: 0% Or 100% Duty-Cycle Wave Output During Pwm Output And Single-Shot Pwm Output Modes
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.17 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes During PWM output or single-shot PWM output mode, if the value ‘FFFF’ is written to the reload 0 or reload 1 register, F/F output will not be inverted, making it possible to produce a 0% or 100% duty-cycle PWM output.
Page 436 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Because the reload 0 register = H'FFFF, a superficial underflow is generated, causing the counter to be loaded with the content of the reload 1 register Enabled (by writing to the enable bit or by Superficial external input) Underflow...
Page 437 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Because the reload 1 register = H'FFFF, a superficial underflow is generated, Enabled causing the counter to be loaded with (by writing to the enable bit Superficial the content of the reload 0 register or by external input) Underflow underflow...
Page 438 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Because the reload 0 register = H'FFFF, a superficial underflow is generated, causing the counter to be loaded with the content of the reload 1 register Enabled (by writing to the enable bit Superficial or by external input) underflow...
Page 439 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) Because the reload 1 register = H'FFFF, a superficial underflow is generated Enabled (by writing to the enable bit Superficial or by external input) Underflow underflow Count clock Enable bit Count down from the reload 0 register set value H'(FFFF-1)
Page 440: Pwm Output Disable Function
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.18 PWM Output Disable Function The microcomputer has the function to forcibly disable outputs from the P160/TO21–P165/TO26, P180/TO29– P185/TO34 and P210/TO37–P215/TO42 that respectively are the output pins for the TOU0_0–TOU0_5, TOU1_0–TOU1_5 and TOU2_0–TOU2_5 timers. This function may be used as a protective function when a fault condition such as short-circuiting is detected during three-phase PWM control.
Page 441 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) IRQ18 TIN33S TML1 (Cap0) P197/TIN33/PWMOFF2 PWMOFF2S P210 (internal) P211 (internal) PO2DIS P212 (internal) P213 (internal) P214 (internal) P215 (internal) P210 (internal) P210/TO37 P211 (internal) P211/TO38 P212 (internal) P212/TO39 P213 (internal) P213/TO40 PO2LVSEL P214 (internal) P214/TO41 PO2LVSEL P215 (internal)
Page 442 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) When using TIN17/PWMOFF1 to disable PWM outputs 1. Write data ‘1’ to the PWMOFF1CR register PWMOFF1SP bit. 2. After 1 above, write data ‘0’ to the PWMOFF1SP bit and then data ‘000,’ ‘001,’ ‘010,’ ‘011,’ ‘10X’ or ‘11X’...
Page 443 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) (3) Using the pin level on ports P160/TO21–P165/TO26, P180/TO29–P185/TO34 or P210/TO37–P215/TO42 to disable PWM outputs The pin level (high or low level) on ports P160/TO21–P165/TO26 may be used to disable outputs from the ports P160/TO21–P165/TO26 that are provided for the PWM outputs of the TOU0_0–TOU0_5 timers.
Page 444: Example Application For Using The 32180 In Motor Control
MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) 10.8.19 Example Application for Using the 32180 in Motor Control The three-channel TOU timers incorporated in the 32180 help to reduce software burdens during motor control. The following shows an example application for using these 32180 timers in motor control. The three-phase motor control waveform is produced by starting TOU in accordance with the fixed 20 kHz TOU startup timing generated by TID.
Page 445 MULTIJUNCTION TIMERS 10.8 TOU (Output-Related 24-Bit Timer) This page is blank for reasons of layout. 32180 Group User’s Manual (Rev.1.0) 10-202...
Page 446: Chapter 11 A-D Converters
CHAPTER 11 A-D CONVERTERS 11.1 Outline of A-D Converters 11.2 A-D Converter Related Registers 11.3 Functional Description of A-D Converters 11.4 Inflow Current Bypass Circuit 11.5 Precautions on Using A-D Converters...
Page 447 A-D Converters 11.1 Outline of A-D Converters 11.1 Outline of A-D Converters The 32180 contains two 10-bit A-D Converters of the successive approximation type (A-D0 and A-D1 Converters). Each A-D Converter has 16 input channels. In addition to performing conversion individually on each channel, the A-D Converter can perform conversion successively on all of N channels (N = 1–16) as a single group.
Page 448 A-D Converters 11.1 Outline of A-D Converters (8) Interrupt and DMA Transfer Request Generation Function An A-D conversion interrupt or DMA transfer request can be generated each time A-D conversion or comparate operation in single mode is completed, as well as when a single-shot scan operation or one cycle of continuous scan operation is completed.
Page 449 A-D Converters 11.1 Outline of A-D Converters Internal data bus 8-bit readout Shifter 10-bit readout AD0DT0 10-bit A-D0 Data Register 0 AD0DT1 AD0SIM0, 1 10-bit A-D0 Data Register 1 A-D0 Single Mode Register AD0DT2 10-bit A-D0 Data Register 2 AD0SCM0, 1 A-D0 Scan Mode Register AD0DT3 10-bit A-D0 Data Register 3...
Page 450 A-D Converters 11.1 Outline of A-D Converters Internal data bus 8-bit readout Shifter 10-bit readout AD1DT0 10-bit A-D1 Data Register 0 AD1DT1 10-bit A-D1 Data Register 1 AD1SIM0, 1 A-D1 Single Mode Register AD1DT2 10-bit A-D1 Data Register 2 A-D1 Scan Mode Register AD1SCM0, 1 AD1DT3 10-bit A-D1 Data Register 3...
Page 451: Conversion Modes
A-D Converters 11.1 Outline of A-D Converters 11.1.1 Conversion Modes The A-D Converters have two conversion mode: “A-D Conversion mode” and “Comparator mode.” (1) A-D Conversion Mode In A-D conversion mode, the analog input voltage on a specified channel is A-D converted. There are two operation modes for A-D conversion mode as will be described later.
Page 452 A-D Converters 11.1 Outline of A-D Converters A-D Successive Approximation Register ADiSAR A-D conversion interrupt or DMA transfer request Conversion i=0,1 ADiINn Completed starts n=0–15 (Note 1) ADiCMP Comparate result ADiCMP=0 (ANn > ADiSAR) A-Di Comparate Data Register ADiCMP=1 (ANn < ADiSAR) Note 1: Comparate operation is started by writing a comparison value to the Successive Approximation Register (ADiSAR) Figure 11.1.4 Operation in Single Mode (Comparate)
Page 453 A-D Converters 11.1 Outline of A-D Converters Table 11.1.2 Registers in Which Scan Mode A-D Conversion Results Are Stored Scan Mode Register 1 Selected channels Selected channels A-D conversion result channel selection for single-shot scan for continuous scan storage register B'0000:0 ADiIN0 ADiIN0...
Page 454: Special Operation Modes
A-D Converters 11.1 Outline of A-D Converters 11.1.3 Special Operation Modes (1) Forcible single mode execution during scan mode In this special operation mode, single mode conversion (A-D conversion or comparate) is forcibly executed on a specified channel during scan mode operation. For A-D conversion mode, the conversion result is stored in the 10-bit A-D Data Register corresponding to the specified channel, whereas for comparate mode, the conversion result is stored in the 10-bit A-D Comparate Data Register.
Page 455 A-D Converters 11.1 Outline of A-D Converters (2) Scan mode start after single mode execution In this special operation mode, scan operation is started subsequently after executing single mode conver- sion (A-D conversion or comparate). To start this mode in software, choose a software trigger using the A-D Scan Mode Register 0 A-D conver- sion start trigger select bit.
Page 456 A-D Converters 11.1 Outline of A-D Converters (3) Conversion restart In this special operation mode, operation being executed in single or scan mode is stopped in the middle and reexecuted from the beginning. When in single mode, set the A-D Single Mode Register 0 A-D conversion start bit to "1" again or enter a hardware trigger during A-D conversion or comparate operation, and the operation that was stopped during execution is executed over again.
Page 457: A-D Converter Interrupt And Dma Transfer Requests
A-D Converters 11.1 Outline of A-D Converters 11.1.4 A-D Converter Interrupt and DMA Transfer Requests The A-D Converter can generate an A-D conversion interrupt or DMA transfer request each time A-D conver- sion, comparate operation, single-shot scan or one cycle of continuous scan mode is completed. The A-D Single Mode Register 0 and A-D Scan Mode Register 0 are used to select between A-D conversion interrupt and DMA transfer requests.
Page 458: A-D Converter Related Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2 A-D Converter Related Registers Shown below is an A-D converter related register map. A-D Converter Related Register Map (1/3) Address +0 address +1 address b7 b8 pages H'0080 0080 A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 11-16 (AD0SIM0)
Page 459 A-D Converters 11.2 A-D Converter Related Registers A-D Converter Related Register Map (2/3) Address +0 address +1 address b7 b8 pages H'0080 00DE (Use inhibited area) 8-bit A-D0 Data Register 7 11-32 (AD08DT7) H'0080 00E0 (Use inhibited area) 8-bit A-D0 Data Register 8 11-32 (AD08DT8) H'0080 00E2...
Page 460 A-D Converters 11.2 A-D Converter Related Registers A-D Converter Related Register Map (3/3) Adrdress +0 address +1 address b7 b8 pages H'0080 0AD0 (Use inhibited area) 8-bit A-D1 Data Register 0 11-32 (AD18DT0) H'0080 0AD2 (Use inhibited area) 8-bit A-D1 Data Register 1 11-32 (AD18DT1) H'0080 0AD4...
Page 461: A-D Single Mode Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.1 A-D Single Mode Registers 0 A-D0 Single Mode Register 0 (AD0SIM0) <Address: H’0080 0080> A-D1 Single Mode Register 0 (AD1SIM0) <Address: H'0080 0A80> ADSTRG1 ADSTRG0 ADSSEL ADSREQ ADSCMP ADSSTP ADSSTT <After reset: H’04> Bit Name Function ADSTRG1 (Note 1)
Page 462 A-D Converters 11.2 A-D Converter Related Registers (2) ADSSEL (A-D Conversion Start Trigger Select) bit (Bit 3) This bit selects whether to use a software or hardware trigger to start A-D conversion during single mode. If a software trigger is selected, A-D conversion is started by setting the ADSSTT (A-D conversion start) bit to "1".
Page 463: A-D Single Mode Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.2 A-D Single Mode Registers 1 A-D0 Single Mode Register 1 (AD0SIM1) <Address: H’0080 0081> A-D1 Single Mode Register 1 (AD1SIM1) <Address: H’0080 0A81> ADSMSL ADSSPD ADSSHSL ADSSHSPD ANSEL <After reset: H’00> Bit Name Function ADSMSL 0: A-D conversion mode...
Page 464 A-D Converters 11.2 A-D Converter Related Registers (1) ADSMSL (A-D Conversion Mode Select) bit (Bit 8) This bit selects A-D conversion mode when the A-D Converter is operating in single mode. Setting this bit to "0" selects A-D conversion mode, and setting this bit to "1" selects comparator mode. (2) ADSSPD (A-D Conversion Speed Select) bit (Bit 9) This bit selects the A-D conversion speed when the A-D Converter is operating in single mode.
Page 465: A-D Scan Mode Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.3 A-D Scan Mode Registers 0 A-D0 Scan Mode Register 0 (AD0SCM0) <Address: H’0080 0084> A-D1 Scan Mode Register 0 (AD1SCM0) <Address: H’0080 0A84> ADCTRG1 ADCMSL ADCTRG0 ADSHIDE ADCREQ ADCCMP ADCSTP ADCSTT <After reset: H’04> Bit Name Function ADCTRG1 (Note 1)
Page 466 A-D Converters 11.2 A-D Converter Related Registers (2) ADCMSL (A-D Scan Mode Select) bit (Bit 1) This bit selects scan mode of the A-D Converter between single-shot scan and continuous scan. Setting this bit to "0" selects single-shot scan mode, where the channels selected with the ANSCAN (scan loop select) bits are sequentially A-D converted and when A-D conversion on all selected channels is com- pleted, the conversion operation stops.
Page 467: A-D Scan Mode Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.4 A-D Scan Mode Registers 1 A-D0 Scan Mode Register 1 (AD0SCM1) <Address: H’0080 0085> A-D1 Scan Mode Register 1 (AD1SCM1) <Address: H’0080 0A85> ADCSPD ADCSHSL ADCSHSPD ADSCAN <After reset: H’00> Bit Name Function No function assigned.
Page 468 A-D Converters 11.2 A-D Converter Related Registers (1) ADCSPD (A-D Conversion Speed Select) bit (Bit 9) This bit selects an A-D conversion speed when the A-D Converter is operating in scan mode. Setting this bit to selects normal speed, and setting this bit to "1" selects double speed. (2) ADCSHSL (A-D Conversion Method Select) bit (Bit 10) This bit enables or disables the sample-and-hold function when the A-D Converter is operating in scan mode.
Page 469: A-D Conversion Speed Control Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.5 A-D Conversion Speed Control Registers A-D0 Conversion Speed Control Register (AD0CVSCR) <Address: H’0080 0087> A-D1 Conversion Speed Control Register (AD1CVSCR) <Address: H’0080 0A87> ADCVSD <After reset: H’00> Bit Name Function 8–14 No function assigned. Fix to "0". ADCVSD (Note 1) 0: Slow mode A-D conversion speed control bit...
Page 470: A-D Disconnection Detection Assist Function Control Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.6 A-D Disconnection Detection Assist Function Control Registers A-D0 Disconnection Detection Assist Function Control Register (AD0DDACR) <Address: H’0080 0086> A-D1 Disconnection Detection Assist Function Control Register (AD1DDACR) <Address: H’0080 0A86> ADDDAEN <After reset: H’00> Bit Name Function 0–6...
Page 471: A-D Disconnection Detection Assist Method Select Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.7 A-D Disconnection Detection Assist Method Select Registers A-D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) <Address: H’0080 008A> A-D1 Disconnection Detection Assist Method Select Register (AD1DDASEL) <Address: H’0080 0A8A> ADDDA ADDDA ADDDA ADDDA ADDDA ADDDA...
Page 472 A-D Converters 11.2 A-D Converter Related Registers Figure 11.2.1 shows an example of A-D disconnection detection assist method in which the conversion start state is set to the AVCC side (i.e., precharge before conversion is selected). Figure 11.2.2 shows an example of A-D disconnection detection assist method in which the conversion start state is set to the AVSS side (i.e., discharge before conversion is selected).
Page 473 A-D Converters 11.2 A-D Converter Related Registers Disconnection detection voltage (without sample-and-hold) 2000 1800 Scan mode: Disconnection detection enabled 1600 Scan mode: Disconnection detection disabled 1400 1200 1000 A-D conversion cycle [kHz] Figure 11.2.3 A-D Disconnection Detection Assist Data (when Discharge Before Conversion Selected) Disconnection detection voltage (without sample-and-hold) 5100 4900...
Page 474: A-D Successive Approximation Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.8 A-D Successive Approximation Registers A-D0 Successive Approximation Register(AD0SAR) <Address: H’0080 0088> A-D1 Successive Approximation Register(AD1SAR) <Address: H’0080 0A88> ADSAR <After reset: Undefined> Bit Name Function 0–5 No function assigned. Fix to "0". 6–15 ADSAR 0: A-D successive approximation value (A-D conversion mode)
Page 475: A-D Comparate Data Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.9 A-D Comparate Data Registers A-D0 Comparate Data Register (AD0CMP) <Address: H’0080 008C> A-D1 Comparate Data Register (AD1CMP) <Address: H’0080 0A8C> ADCMP0 ADCMP1 ADCMP2 ADCMP3 ADCMP4 ADCMP5 ADCMP6 ADCMP7 ADCMP8 ADCMP9 ADCMP10 ADCMP11 ADCMP12 ADCMP13 ADCMP14 ADCMP15 <After reset: Undefined>...
Page 476: 10-Bit A-D Data Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.10 10-bit A-D Data Registers 10-bit A-D0 Data Register 0(AD0DT0) <Address: H’0080 0090> 10-bit A-D0 Data Register 1(AD0DT1) <Address: H’0080 0092> 10-bit A-D0 Data Register 2(AD0DT2) <Address: H’0080 0094> 10-bit A-D0 Data Register 3(AD0DT3) <Address: H’0080 0096>...
Page 477: 8-Bit A-D Data Registers
A-D Converters 11.2 A-D Converter Related Registers 11.2.11 8-bit A-D Data Registers 8-bit A-D0 Data Register 0(AD08DT0) <Address: H’0080 00D1> 8-bit A-D0 Data Register 1(AD08DT1) <Address: H’0080 00D3> 8-bit A-D0 Data Register 2(AD08DT2) <Address: H’0080 00D5> 8-bit A-D0 Data Register 3(AD08DT3) <Address: H’0080 00D7>...
Page 478: Functional Description Of A-D Converters
A-D Converters 11.3 Functional Description of A-D Converters 11.3 Functional Description of A-D Converters 11.3.1 How to Find Analog Input Voltages The A-D Converters perform A-D conversion using a 10-bit successive approximation method as will be de- scribed later. The equation shown below is used to calculate the actual analog input voltage from the digital value obtained by executing A-D conversion.
Page 479: A-D Conversion By Successive Approximation Method
A-D Converters 11.3 Functional Description of A-D Converters 11.3.2 A-D Conversion by Successive Approximation Method The A-D Converters use an A-D conversion start trigger (software or hardware) as they start A-D conversion. Once A-D conversion begins, the following operation is automatically performed. 1.
Page 480: Comparator Operation
A-D Converters 11.3 Functional Description of A-D Converters The conversion result is stored in the 10-bit A-D Data Register (AD0DTn, AD1DTn) corresponding to each converted channel. There is also an 8-bit A-D Data Register (AD08DTn, AD18DTn) for each channel, from which the 8 high-order bits of the 10-bit conversion result can be read out.
Page 481: Calculating The A-D Conversion Time
A-D Converters 11.3 Functional Description of A-D Converters 11.3.4 Calculating the A-D Conversion Time The A-D conversion time is expressed by the sum of dummy cycle time and actual execution cycle time. The following shows each time factor necessary to calculate the conversion time. 1.
Page 482 A-D Converters 11.3 Functional Description of A-D Converters Table 11.3.1 Conversion Clock Periods in A-D Conversion Mode Unit: BCLK Conversion speed Start dummy (Note 1) Execution cycle End dummy Scan to scan dummy (Note 2) Slow mode Normal speed Double speed Fast mode Normal speed Double speed...
Page 483 A-D Converters 11.3 Functional Description of A-D Converters (3) Calculating the conversion time during comparator mode The following schematically shows the method for calculating the conversion time during comparator mode. Convert operation Transferred to the A-D conversion Completed starts comparate data register start trigger Start dummy Execution cycle...
Page 484: Accuracy Of A-D Conversion
A-D Converters 11.3 Functional Description of A-D Converters 11.3.5 Accuracy of A-D Conversion The accuracy of the A-D Converters is indicated by an absolute accuracy. The absolute accuracy refers to a difference expressed by LSB between the output code obtained by A-D converting the analog input voltages and the output code expected for an A-D converter with ideal characteristics.
Page 485 A-D Converters 11.3 Functional Description of A-D Converters H'00B Ideal A-D conversion characteristics H'00A H'009 H'008 +2 LSB H'007 H'006 A-D conversion characteristics H'005 with infinite resolution H'004 H'003 -2 LSB H'002 H'001 H'000 → Analog input voltage [mV] Figure 11.3.7 Absolute Accuracy of A-D Converters 32180 Group User's Manual (Rev.1.0) 11-40...
Page 486: Inflow Current Bypass Circuit
A-D Converters 11.4 Inflow Current Bypass Circuit 11.4 Inflow Current Bypass Circuit If when the A-D Converter is A-D converting a selected analog input an overvoltage exceeding the converter’s absolute maximum rating is applied to any unselected analog input, the selector for the unselected analog input is inadvertently turned on by that overvoltage.
Page 487 A-D Converters 11.4 Inflow Current Bypass Circuit Leakage current generated Leakage current Unselected channel generated Unaffected by leakage To the internal logic of the A-D Converter GND - 0.7V or less Selected channel Sensor input Assist circuit Figure 11.4.3 Example of an Inflow Current Bypass Circuit where GND – 0.7 V or Less is Applied Table 11.4.1 Accuracy Errors (Actual Performance Values) when Current is Injected into AD0IN0 Accuracy error on overcurrent injected ports (Unit: LSB) Analog input pin...
Page 488: Precautions On Using A-D Converters
A-D Converters 11.5 Precautions on Using A-D Converters 11.5 Precautions on Using A-D Converters • Forcible termination during scan operation If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP or AD1CSTP) to "1" during scan mode operation and the A-D data register for the channel that was in the middle of conversion is accessed for read, the read value shows the last conversion result that had been transferred to the data register before the conversion was forcibly terminated.
Page 489 A-D Converters 11.5 Precautions on Using A-D Converters (a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended) Assuming the R1 in Figure 11.5.1 is infinitely large and that the current necessary to charge the internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have.
Page 490 A-D Converters 11.5 Precautions on Using A-D Converters Table 11.5.1 Sampling Time (in Which C2 Needs to Be Charged) Conversion start method Conversion speed Sampling time for the first bit Sampling time for the second and subsequent bits Single mode Slow mode Normal speed 27.5BCLK...
Page 491 A-D Converters 11.5 Precautions on Using A-D Converters This page is blank for reasons of layout. 32180 Group User's Manual (Rev.1.0) 11-46...
Page 492: Chapter 12 Serial I/O
CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O 12.2 Serial I/O Related Registers 12.3 Transmit Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.5 Precautions on Using CSIO Mode 12.6 Transmit Operation in UART Mode 12.7 Receive Operation in UART Mode 12.8 Fixed Period Clock Output Function 12.9 Precautions on Using UART Mode...
Page 493 Serial I/O 12.1 Outline of Serial I/O 12.1 Outline of Serial I/O The 32180 contains a total of six serial I/O channels, SIO0–SIO5. Channels SIO0, SIO1, SIO4 and SIO5 can be selected between CSIO mode (clock-synchronous serial I/O) and UART mode (clock-asynchronous serial I/O). Channels SIO2 and SIO3 are UART mode only.
Page 494 Serial I/O 12.1 Outline of Serial I/O Table 12.1.2 Interrupt Generation Functions of Serial I/O Serial I/O Interrupt Request Source ICU Interrupt Sources SIO0 transmit buffer empty or transmission finished SIO0 transmit interrupt SIO0 reception finished or receive error SIO0 receive interrupt SIO1 transmit buffer empty or transmission finished SIO1 transmit interrupt SIO1 reception finished or receive error...
Page 495 Serial I/O 12.1 Outline of Serial I/O SIO0 SIO0 Transmit Buffer Register Transmit interrupt request To the Interrupt SIO0 Transmit Shift Register TXD0 Receive interrupt request Controller (ICU) Transmit/ Receive Control Transmit DMA transfer request To DMA3, DMA4 Circuit RXD0 SIO0 Receive Shift Register Receive DMA transfer request To DMA4...
Page 496 Serial I/O 12.2 Serial I/O Related Registers 12.2 Serial I/O Related Registers Shown below is a serial I/O related register map. Serial I/O Related Register Map Address +0 address +1 address b7 b8 pages H'0080 0100 SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register 12-9 (SI23STAT)
Page 497: Sio Interrupt Related Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.1 SIO Interrupt Related Registers The SIO interrupt related registers are used to control the interrupt request signals output from SIO to the Interrupt Controller (ICU), as well as select the source of each interrupt request. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested.
Page 498 Serial I/O 12.2 Serial I/O Related Registers Example for clearing interrupt request status Interrupt request status Initial state Interrupt request Bit 6 event occurs Bit 4 event occurs Write to the interrupt request status Only bit 6 cleared Bit 4 data retained Program example •...
Page 499 Serial I/O 12.2 Serial I/O Related Registers (3) Selecting the source of an interrupt request The interrupt request signals sent from each SIO to the Interrupt Controller (ICU) are broadly classified into transmit interrupts and receive interrupts. Transmit interrupt requests can be generated when the transmit buffer is empty or transmission is finished, and the receive interrupt requests can be generated when recep- tion is finished or an receive error is detected, as selected by the Interrupt Source Select Registers (SI03SEL, SI45SEL).
Page 500 Serial I/O 12.2 Serial I/O Related Registers SIO23 Interrupt Request Status Register (SI23STAT) <Address: H’0080 0100> IRQT2 IRQR2 IRQT3 IRQR3 <After reset: H’00> Bit Name Function 0–3 No function assigned. Fix to "0". IRQT2 0: Interrupt not requested R (Note 1) SIO2 transmit interrupt request status bit 1: Interrupt requested IRQR2...
Page 501 Serial I/O 12.2 Serial I/O Related Registers SIO03 Interrupt Request Enable Register (SI03EN) <Address: H’0080 0101> T0EN R0EN T1EN R1EN T2EN R2EN T3EN R3EN <After reset: H’00> Bit Name Function T0EN 0: Mask (disable) interrupt request SIO0 transmit interrupt request enable bit 1: Enable interrupt request R0EN 0: Mask (disable) interrupt request...
Page 502 Serial I/O 12.2 Serial I/O Related Registers SIO03 Interrupt Source Select Register (SI03EN) <Address: H’0080 0102> IST0 IST1 IST2 IST3 ISR0 ISR1 ISR2 ISR3 <After reset: H’00> Bit Name Function IST0 0: Transmit buffer empty interrupt SIO0 transmit interrupt request source select bit 1: Transmission finished interrupt IST1 0: Transmit buffer empty interrupt...
Page 503 Serial I/O 12.2 Serial I/O Related Registers (1) SIOn transmit interrupt request source select bit [When set to "0"] The transmit buffer empty interrupt is selected. A transmit buffer empty interrupt request is generated when data is transferred from the transmit buffer register to the transmit shift register. Also, a transmit buffer empty interrupt request is generated when the TEN (Transmit Enable) bit is set to "1"...
Page 504 Serial I/O 12.2 Serial I/O Related Registers <SI03SEL : H'0080 0102> <SI23STAT : H'0080 0100> <SI03EN : H'0080 0101> Data bus SIO2 transmit buffer empty SIO2 transmission finished IRQT2 IST2 4-source inputs SIO2, 3 T2EN transmit/receive (Level) interrupt requests SIO2 reception finished SIO2 receive error IRQR2...
Page 505: Sio Transmit Control Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.2 SIO Transmit Control Registers SIO0 Transmit Control Register (S0TCNT) <Address: H'0080 0110> SIO1 Transmit Control Register (S1TCNT) <Address: H'0080 0120> SIO2 Transmit Control Register (S2TCNT) <Address: H'0080 0130> SIO3 Transmit Control Register (S3TCNT) <Address: H'0080 0140>...
Page 506: Sio Transmit/Receive Mode Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.3 SIO Transmit/Receive Mode Registers SIO0 Transmit/Receive Mode Register (S0MOD) <Address: H'0080 0111> SIO1 Transmit/Receive Mode Register (S1MOD) <Address: H'0080 0121> SIO2 Transmit/Receive Mode Register (S2MOD) <Address: H'0080 0131> SIO3 Transmit/Receive Mode Register (S3MOD) <Address: H'0080 0141>...
Page 507 Serial I/O 12.2 Serial I/O Related Registers (4) PSEL (Odd/Even Parity Select) bit (Bit 13) This bit is effective during UART mode. When parity is enabled (bit 14 = "1"), use this bit to select the parity attribute (whether odd or even). Setting this bit to "0" selects an odd parity, and setting this bit to "1" selects an even parity.
Page 508 Serial I/O 12.2 Serial I/O Related Registers ST : Start bit PAR : Parity bit : One frame equivalent b : Data bits SP : Stop bit Direction of transfer • Clock-synchronous mode (Note 1) (Note 2) • 7-bit UART mode (Note 2) (Note 1) •...
Page 509: Sio Transmit Buffer Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.4 SIO Transmit Buffer Registers SIO0 Transmit Buffer Register (S0TXB) <Address: H'0080 0112> SIO1 Transmit Buffer Register (S1TXB) <Address: H'0080 0122> SIO2 Transmit Buffer Register (S2TXB) <Address: H'0080 0132> SIO3 Transmit Buffer Register (S3TXB) <Address: H'0080 0142>...
Page 510: Sio Receive Buffer Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.5 SIO Receive Buffer Registers SIO0 Receive Buffer Register (S0RXB) <Address: H'0080 0114> SIO1 Receive Buffer Register (S1RXB) <Address: H'0080 0124> SIO2 Receive Buffer Register (S2RXB) <Address: H'0080 0134> SIO3 Receive Buffer Register (S3RXB) <Address: H'0080 0144>...
Page 511: Sio Receive Control Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.6 SIO Receive Control Registers SIO0 Receive Control Register (S0RCNT) <Address: H'0080 0116> SIO1 Receive Control Register (S1RCNT) <Address: H'0080 0126> SIO2 Receive Control Register (S2RCNT) <Address: H'0080 0136> SIO3 Receive Control Register (S3RCNT) <Address: H'0080 0146>...
Page 512 Serial I/O 12.2 Serial I/O Related Registers (1) RSTAT (Receive Status) bit (Bit 1) [Set condition] This bit is set to "1" by a start of receive operation. When this bit = "1", the serial I/O is receiving data. [Clear condition] This bit is cleared to "0"...
Page 513 Serial I/O 12.2 Serial I/O Related Registers (6) FLM (Framing Error) bit (Bit 6) This bit is effective in only UART mode. It is fixed to "0" during CSIO mode. [Set condition] The FLM (Framing Error) bit is set to "1" when the number of received bits does not agree with one that was set by the SIO Transmit/Receive Mode Register.
Page 514: Sio Baud Rate Registers
Serial I/O 12.2 Serial I/O Related Registers 12.2.7 SIO Baud Rate Registers SIO0 Baud Rate Register (S0BAUR) <Address: H'0080 0117> SIO1 Baud Rate Register (S1BAUR) <Address: H'0080 0127> SIO2 Baud Rate Register (S2BAUR) <Address: H'0080 0137> SIO3 Baud Rate Register (S3BAUR) <Address: H'0080 0147>...
Page 515: Transmit Operation In Csio Mode
Serial I/O 12.3 Transmit Operation in CSIO Mode 12.3 Transmit Operation in CSIO Mode 12.3.1 Setting the CSIO Baud Rate The baud rate (data transfer rate) in CSIO mode is determined by a transmit/receive shift clock. The clock source from which a transmit/receive shift clock derives is selected from the internal clock f(BCLK) or external clock.
Page 516: Initializing Csio Transmission
Serial I/O 12.3 Transmit Operation in CSIO Mode 12.3.2 Initializing CSIO Transmission To transmit data in CSIO mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to CSIO mode. •...
Page 517 Serial I/O 12.3 Transmit Operation in CSIO Mode Initialize CSIO transmission • Set the register to CSIO mode Set SIO Transmit/Receive Mode Register • Select the internal or external clock Set SIO Transmit Control Register • Select the clock divider divide-by ratio (Note 1) Serial I/O related registers •...
Page 518: Starting Csio Transmission
Serial I/O 12.3 Transmit Operation in CSIO Mode 12.3.3 Starting CSIO Transmission The serial I/O starts a transmit operation when all of the following conditions are met after being initialized. (1) Transmit conditions when CSIO mode internal clock is selected •...
Page 519: Processing At End Of Csio Transmission
Serial I/O 12.3 Transmit Operation in CSIO Mode 12.3.5 Processing at End of CSIO Transmission When data transmission finishes, the following operation is automatically performed in hardware. (1) When not transmitting successively • The transmit status bit is cleared to "0". (2) When transmitting successively •...
Page 520 Serial I/O 12.3 Transmit Operation in CSIO Mode The following processing is automatically performed in hardware. CSIO transmit operation starts Transmit conditions met? (Note 1) Transmit interrupt request • Transfer the content of the transmit buffer to the transmit shift register •...
Page 521: Example Of Csio Transmit Operation
Serial I/O 12.3 Transmit Operation in CSIO Mode 12.3.8 Example of CSIO Transmit Operation The following shows a typical transmit operation in CSIO mode. <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI <CSIO on transmit side> Internal clock selected External clock selected (Internal transfer clock) Transmit clock...
Page 522 Serial I/O 12.3 Transmit Operation in CSIO Mode <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI <CSIO on transmit side> Internal clock selected External clock selected (Internal transfer clock) Transmit clock (SCLKO) Transmit enable bit Write to the Write to the transmit buffer transmit buffer...
Page 523: Receive Operation In Csio Mode
Serial I/O 12.4 Receive Operation in CSIO Mode 12.4 Receive Operation in CSIO Mode 12.4.1 Initialization for CSIO Reception To receive data in CSIO mode, initialize the serial I/O following the procedure described below. Note, however, that because the receive shift clock is derived by an operation of the transmit circuit, transmit operation must always be executed even when the serial I/O is used for only receiving data.
Page 524 Serial I/O 12.4 Receive Operation in CSIO Mode (8) Selecting pin functions Because the serial I/O related pins serve dual purposes, set the pin functions for use as SIO pins or input/ output ports. (See Chapter 8, “Input/Output Ports and Pin Functions.”) Initialize CSIO reception •...
Page 525: Starting Csio Reception
Serial I/O 12.4 Receive Operation in CSIO Mode 12.4.2 Starting CSIO Reception The serial I/O starts receive operation when all of the following conditions are met after being initialized. (1) Receive conditions when CSIO mode internal clock is selected • The SIO Receive Control Register receive enable bit is set to "1". •...
Page 526: About Successive Reception
Serial I/O 12.4 Receive Operation in CSIO Mode 12.4.4 About Successive Reception If the following conditions are met when data reception has finished, data may be received successively. • The receive enable bit is set to "1". • Transmit conditions are met. •...
Page 527: Flags Showing The Status Of Csio Receive Operation
Serial I/O 12.4 Receive Operation in CSIO Mode 12.4.5 Flags Showing the Status of CSIO Receive Operation There are following flags that indicate the status of receive operation during CSIO mode: • SIO Receive Control Register receive status bit • SIO Receive Control Register reception finished bit •...
Page 528: Example Of Csio Receive Operation
Serial I/O 12.4 Receive Operation in CSIO Mode 12.4.6 Example of CSIO Receive Operation The following shows a typical receive operation in CSIO mode. <CSIO on transmit side> <CSIO on receive side> SCLKO SCLKI <CSIO on receive side> Internal clock selected External clock selected Receive clock Clock stops...
Page 529 Serial I/O 12.4 Receive Operation in CSIO Mode <CSIO on receive side> <CSIO on transmit side> SCLKO SCLKI Internal clock selected External clock selected <CSIO on receive side> Receive clock (SCLKI) Cleared Receive enable bit First data reception Next data reception completed completed Receive buffer not read...
Page 530: Precautions On Using Csio Mode
Serial I/O 12.5 Precautions on Using CSIO Mod 12.5 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating.
Page 531: Transmit Operation In Uart Mode
Serial I/O 12.6 Transmit Operation in UART Mode 12.6 Transmit Operation in UART Mode 12.6.1 Setting the UART Baud Rate The baud rate (data transfer rate) in UART mode is determined by a transmit/receive shift clock. During UART mode, the source for this transmit/receive shift clock is always the internal clock no matter how the internal/ external clock select bit (SIO Transmit/Receive Mode Register bit 11) is set.
Page 532 Serial I/O 12.6 Transmit Operation in UART Mode Table 12.6.1 Transfer Data in UART Mode Bit Name Content ST (start bit) Indicates the beginning of data transmission. This is a low-level signal of a one bit period, which is added immediately preceding the transmit data. Bits 0–8 (character bits) Transmit/receive data transferred via serial I/O.
Page 533: Initializing Uart Transmission
Serial I/O 12.6 Transmit Operation in UART Mode 12.6.3 Initializing UART Transmission To transmit data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register • Set the register to UART mode. •...
Page 534 Serial I/O 12.6 Transmit Operation in UART Mode Initialize UART transmission • Set the register to UART mode • Set parity (when enabled, select odd/even) Set SIO Transmit/Receive Mode Register • Set the stop bit length • Set the character length •...
Page 535: Starting Uart Transmission
Serial I/O 12.6 Transmit Operation in UART Mode 12.6.4 Starting UART Transmission The serial I/O starts a transmit operation when all of the following conditions are met after being initialized. • SIO Transmit Control Register TEN (Transmit Enable) bit is set to "1" (Note 1). •...
Page 536: Transmit Dma Transfer Request
Serial I/O 12.6 Transmit Operation in UART Mode (2) Transmission finished interrupt If the transmission finished interrupt was selected using the SIO Interrupt Request Source Select Register, a transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.
Page 537: Example Of Uart Transmit Operation
Serial I/O 12.6 Transmit Operation in UART Mode 12.6.9 Example of UART Transmit Operation The following shows a typical transmit operation in UART mode. <UART on transmit side> <UART on receive side> <UART on transmit side> Transmit enable bit Write to the transmit buffer Cleared register...
Page 538 Serial I/O 12.6 Transmit Operation in UART Mode <UART on transmit side> <UART on receive side> <UART on transmit side> Transmit enable bit Cleared Write to the Write to the transmit buffer transmit buffer register register (First data) (Next data) Transmit buffer empty bit Cleared when transfer of...
Page 539: Receive Operation In Uart Mode
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7 Receive Operation in UART Mode 12.7.1 Initialization for UART Reception To receive data in UART mode, initialize the serial I/O following the procedure described below. (1) Setting SIO Transmit/Receive Mode Register •...
Page 540 SERIAL I/O 12.7 Receive Operation in UART Mode Initialize UART reception • Set the register to UART mode • Set parity (when enabled, select odd/even) Set SIO Transmit/Receive Mode Register • Set the stop bit length • Set the character length •...
Page 541: Starting Uart Reception
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.2 Starting UART Reception The serial I/O starts receive operation when all of the following conditions are met after being initialized. • SIO Receive Control Register receive enable bit is set to "1" •...
Page 542 SERIAL I/O 12.7 Receive Operation in UART Mode The following processing is automatically performed in hardware. UART receive operation starts Receive conditions met ? Start bit detected normally ? Set the receive status bit to "1" Receive data Overrun error ? Transfer data from the SIO Receive Shift Register to the SIO Receive Buffer Register Set the SIO Receive Control...
Page 543: Example Of Uart Receive Operation
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.4 Example of UART Receive Operation The following shows a typical receive operation in UART mode. <UART on receive side> <UART on transmit side> Internal clock selected <UART on receive side> Receive enable bit (SIO Receive Control Register) Cleared SP SP...
Page 544 SERIAL I/O 12.7 Receive Operation in UART Mode <UART on receive side> <UART on transmit side> <UART on receive side> Receive enable bit SIO Receive Control Register) First data reception Next data reception completed completed Receive buffer not read during this interval Reception finished bit (Note 5) Overrun error bit...
Page 545: Start Bit Detection During Uart Reception
SERIAL I/O 12.7 Receive Operation in UART Mode 12.7.5 Start Bit Detection during UART Reception The start bit is sampled synchronously with the internal BRG output. If the received signal remains low for 8 BRG output cycles after the falling edge of the start bit, the CPU recognizes that part of the received signal as the start bit and starts latching the received data another 8 cycles after that, beginning with the LSB (first bit).
Page 546: Fixed Period Clock Output Function
Serial I/O 12.8 Fixed Period Clock Output Function 12.8 Fixed Period Clock Output Function When using SIO0, SIO1, SIO4 or SIO5 in UART mode, the relevant port (P84, P87, P65 or P66) can be switched for use as an SCLKO0, SCLKO1, SCLKO4 or SCLKO5 pin, respectively. That way, a BRG output clock divided by 2 can be output from the SCLKO pin.
Page 547: Precautions On Using Uart Mode
Serial I/O 12.9 Precautions on Using UART Mode 12.9 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating.
Page 548: Chapter 13 Can Module
CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module 13.2 CAN Module Related Registers 13.3 CAN Protocol 13.4 Initializing the CAN Module 13.5 Transmitting Data Frames 13.6 Receiving Data Frames 13.7 Transmitting Remote Frames 13.8 Receiving Remote Frames 13.9 Precautions about CAN Module...
Page 549 CAN MODULE 13.1 Outline of the CAN Module 13.1 Outline of the CAN Module The 32180 contains two-channel Full CAN modules compliant with CAN (Controller Area Network) Specification V2.0 B Active. These CAN modules each have 16 message slots and three mask registers, effective use of which helps to reduce the data processing load of the CPU.
Page 550 CAN MODULE 13.1 Outline of the CAN Module Table 13.1.3 Interrupt Requests Generated by CAN Modules CAN Module Interrupt Request Source ICU Input Interrupt Source CAN0 transmission completed CAN0 transmit/receive & error interrupt CAN1 transmission completed CAN1 transmit/receive & error interrupt CAN0 reception completed CAN0 transmit/receive &...
Page 551 CAN MODULE 13.2 CAN Module Related Registers 13.2 CAN Module Related Registers Shown below is a CAN module related register map. CAN Module Related Register Map (1/11) Address +0 address +1 address See pages b7 b8 H'0080 1000 CAN0 Control Register 13-15 (CAN0CNT) H'0080 1002...
Page 552 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (2/11) Address +0 address +1 address See pages b7 b8 H'0080 1050 CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register 13-53 (C0MSL0CNT) (C0MSL1CNT) H'0080 1052 CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register 13-53...
Page 553 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (3/11) Address +0 address +1 address See pages b7 b8 H'0080 1130 CAN0 Message Slot 3 Standard ID0 CAN0 Message Slot 3 Standard ID1 13-57 (C0MSL3SID0) (C0MSL3SID1) 13-58 H'0080 1132 CAN0 Message Slot 3 Extended ID0 CAN0 Message Slot 3 Extended ID1...
Page 554 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (4/11) Address +0 address +1 address See pages b7 b8 H'0080 1170 CAN0 Message Slot 7 Standard ID0 CAN0 Message Slot 7 Standard ID1 13-57 (C0MSL7SID0) (C0MSL7SID1) 13-58 H'0080 1172 CAN0 Message Slot 7 Extended ID0 CAN0 Message Slot 7 Extended ID1...
Page 555 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (5/11) Address +0 address +1 address See pages b7 b8 H'0080 11B0 CAN0 Message Slot 11 Standard ID0 CAN0 Message Slot 11 Standard ID1 13-57 (C0MSL11SID0) (C0MSL11SID1) 13-58 H'0080 11B2 CAN0 Message Slot 11 Extended ID0 CAN0 Message Slot 11 Extended ID1...
Page 556 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (6/11) Address +0 address +1 address See pages b7 b8 H'0080 11F0 CAN0 Message Slot 15 Standard ID0 CAN0 Message Slot 15 Standard ID1 13-57 (C0MSL15SID0) (C0MSL15SID1) 13-58 H'0080 11F2 CAN0 Message Slot 15 Extended ID0 CAN0 Message Slot 15 Extended ID1...
Page 557 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (7/11) Address +0 address +1 address See pages b7 b8 H'0080 1440 CAN1 Single-Shot Mode Control Register 13-52 (CAN1SSMODE) H'0080 1442 (Use inhibited area) H'0080 1444 CAN1 Single-Shot Interrupt Request Status Register 13-33 (CAN1SSIST) H'0080 1446...
Page 558 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (8/11) Address +0 address +1 address See pages b7 b8 H'0080 1520 CAN1 Message Slot 2 Standard ID0 CAN1 Message Slot 2 Standard ID1 13-57 (C1MSL2SID0) (C1MSL2SID1) 13-58 H'0080 1522 CAN1 Message Slot 2 Extended ID0 CAN1 Message Slot 2 Extended ID1...
Page 559 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (9/11) Address +0 address +1 address See pages b7 b8 H'0080 1560 CAN1 Message Slot 6 Standard ID0 CAN1 Message Slot 6 Standard ID1 13-57 (C1MSL6SID0) (C1MSL6SID1) 13-58 H'0080 1562 CAN1 Message Slot 6 Extended ID0 CAN1 Message Slot 6 Extended ID1...
Page 560 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (10/11) Address +0 address +1 address See pages b7 b8 H'0080 15A0 CAN1 Message Slot 10 Standard ID0 CAN1 Message Slot 10 Standard ID1 13-57 (C1MSL10SID0) (C1MSL10SID1) 13-58 H'0080 15A2 CAN1 Message Slot 10 Extended ID0 CAN1 Message Slot 10 Extended ID1...
Page 561 CAN MODULE 13.2 CAN Module Related Registers CAN Module Related Register Map (11/11) Address +0 address +1 address See pages b7 b8 H'0080 15E0 CAN1 Message Slot 14 Standard ID0 CAN1 Message Slot 14 Standard ID1 13-57 (C1MSL14SID0) (C1MSL14SID1) 13-58 H'0080 15E2 CAN1 Message Slot 14 Extended ID0 CAN1 Message Slot 14 Extended ID1...
Page 562: Can Control Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.1 CAN Control Registers CAN0 Control Register (CAN0CNT) <Address: H’0080 1000> CAN1 Control Register (CAN1CNT) <Address: H’0080 1400> FRST <After reset: H’0011> Bit Name Function 0–3 No function assigned. Fix to "0". 0: Enable normal operation R(Note 1) Return bus off bit 1: Request clearing of error counter...
Page 563 CAN MODULE 13.2 CAN Module Related Registers (1) RBO (Return Bus Off) bit (Bit 4) Setting this bit to "1" clears the CAN Receive Error Count Register (CANnREC) and CAN Transmit Error Count Register (CANnTEC) to H'00 and forcibly places the CAN module into an error active state. This bit is cleared when the CAN module goes to an error active state.
Page 564 CAN MODULE 13.2 CAN Module Related Registers • Procedure for entering BasicCAN mode Follow the procedure below during initialization: 1) Set the ID for slots 14 and 15 and the local mask registers A and B. (We recommend setting the same value.) 2) Set the frame types to be handled by slots 14 and 15 (standard or extended) in the CAN Extended ID Register.
Page 565: Can Status Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.2 CAN Status Registers CAN0 Status Register (CAN0STAT) <Address: H’0080 1002> CAN1 Status Register (CAN1STAT) <Address: H’0080 1402> <After reset: H’0100> Bit Name Function No function assigned. Fix to "0". 0: Not bus off –...
Page 566 CAN MODULE 13.2 CAN Module Related Registers (1) BOS (Bus Off Status) bit (Bit 1) When BOS bit = "1", it means that the CAN module is in a buss off state. [Set condition] This bit is set to "1" when the transmit error count register value exceeded 255 and a bus off state is entered.
Page 567 CAN MODULE 13.2 CAN Module Related Registers (6) CRS (CAN Reset Status) bit (Bit 7) When CRS bit = "1", it means that the protocol control unit is in a reset state. [Set condition] This bit is set to "1" when the CAN protocol control unit is in a reset state. [Clear condition] This bit is cleared by clearing the CAN Control Register RST (CAN reset) and FRST bits to "0".
Page 568: Can Frame Format Select Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.3 CAN Frame Format Select Registers CAN0 Frame Format Select Register (CAN0FFS) <Address: H’0080 1004> CAN1 Frame Format Select Register (CAN1FFS) <Address: H’0080 1404> FFE0 FFE1 FFE2 FFE3 FFE4 FFE5 FFE6 FFE7 FFE8 FFE9 FFE10 FFE11...
Page 569: Can Configuration Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.4 CAN Configuration Registers CAN0 Configuration Register (CAN0CONF) <Address: H'0080 1006> CAN1 Configuration Register (CAN1CONF) <Address: H'0080 1406> <After reset: H’0000> Bit Name Function 0–1 00: SJW = 1Tq reSynchronization Jump Width setting bit 01: SJW = 2Tq 10: SJW = 3Tq 11: SJW = 4Tq...
Page 570 CAN MODULE 13.2 CAN Module Related Registers (1) SJW bits (Bits 0–1) These bits set the reSynchronization Jump Width. (2) PH2 bits (Bits 2–4) These bits set the width of Phase Segment2. (3) PH1 bits (Bits 5–7) These bits set the width of Phase Segment1. (4) PRB bits (Bits 8–10) These bits set the width of Propagation Segment.
Page 571: Can Timestamp Count Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.5 CAN Timestamp Count Registers CAN0 Timestamp Count Register (CAN0TSTMP) <Address: H’0080 1008> CAN1 Timestamp Count Register (CAN1TSTMP) <Address: H’0080 1408> CANTSTMP <After reset: H’0000> Bit Name Function 0–15 CANTSTMP 16-bit timestamp count value –...
Page 572: Can Error Count Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.6 CAN Error Count Registers CAN0 Receive Error Count Register (CAN0REC) <Address: H’0080 100A> CAN1 Receive Error Count Register (CAN1REC) <Address: H’0080 140A> <After reset: H’00> Bit Name Function 0–7 Receive error count value –...
Page 573: Can Baud Rate Prescalers
CAN MODULE 13.2 CAN Module Related Registers 13.2.7 CAN Baud Rate Prescalers CAN0 Baud Rate Prescaler (CAN0BRP) <Address: H’0080 1016> CAN1 Baud Rate Prescaler (CAN1BRP) <Address: H’0080 1416> <After reset: H’00> Bit Name Function 0–7 Baud rate prescaler value This register sets the Tq period of CAN. The CAN baud rate is determined by (Tq period × number of Tq’s in one bit). Tq period = (BRP + 1) / (CPU clock/2) CAN transfer baud rate = Tq period ×...
Page 574: Can Interrupt Related Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.8 CAN Interrupt Related Registers The CAN interrupt related registers are used to control the interrupt request signals output to the Interrupt Control- ler by CAN. (1) Interrupt request status bit This status bit is used to determine whether an interrupt is requested. When an interrupt request occurs, this bit is set in hardware (cannot be set in software).
Page 575 CAN MODULE 13.2 CAN Module Related Registers Example for clearing interrupt request status Interrupt request status Initial state Interrupt request Event occurs on bit 6 Event occurs on bit 4 Write to the interrupt request status Only bit 6 cleared Bit 4 data retained Program example •...
Page 576 CAN MODULE 13.2 CAN Module Related Registers CAN0 Slot Interrupt Request Status Register (CAN0SLIST) <Address: H’0080 100C> CAN1 Slot Interrupt Request Status Register (CAN1SLIST) <Address: H’0080 140C> SSB0 SSB1 SSB2 SSB3 SSB4 SSB5 SSB6 SSB7 SSB8 SSB9 SSB10 SSB11 SSB12 SSB13 SSB14 SSB15...
Page 577 CAN MODULE 13.2 CAN Module Related Registers CAN0 Slot Interrupt Request Enable Register (CAN0SLIEN) <Address: H’0080 1010> CAN1 Slot Interrupt Request Enable Register (CAN1SLIEN) <Address: H’0080 1410> IRB0 IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15...
Page 578 CAN MODULE 13.2 CAN Module Related Registers CAN0 Error Interrupt Request Status Register (CAN0ERIST) <Address: H’0080 1014> CAN1 Error Interrupt Request Status Register (CAN1ERIST) <Address: H’0080 1414> BEIS EPIS EOIS <After reset: H’00> Bit Name Function 0–4 No function assigned. Fix to "0". BEIS 0: Interrupt not requested R(Note 1)
Page 579 CAN MODULE 13.2 CAN Module Related Registers CAN0 Error Interrupt Request Enable Register (CAN0ERIEN) <Address: H’0080 1015> CAN1 Error Interrupt Request Enable Register (CAN1ERIEN) <Address: H’0080 1415> BEIEN EPIEN EOIEN <After reset: H’00> Bit Name Function 8–12 No function assigned. Fix to "0". BEIEN 0: Mask (disable) interrupt request CAN bus error interrupt request enable bit...
Page 580 CAN MODULE 13.2 CAN Module Related Registers CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST) <address: H’0080 1044> CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST) <Address: H’0080 1444> SSIST0 SSIST1 SSIST2 SSIST3 SSIST4 SSIST5 SSIST6 SSIST7 SSIST8 SSIST9 SSIST10 SSIST11 SSIST12 SSIST13 SSIST14 SSIST15 <After reset: H’0000>...
Page 581 CAN MODULE 13.2 CAN Module Related Registers CAN0 Single-Shot Interrupt Request Enable Register (CAN0SSIEN) <Address: H’0080 1048> CAN1 Single-Shot Interrupt Request Enable Register (CAN1SSIEN) <Address: H’0080 1448> SSIEN0 SSIEN1 SSIEN2 SSIEN3 SSIEN4 SSIEN5 SSIEN6 SSIEN7 SSIEN8 SSIEN9 SSIEN10 SSIEN11 SSIEN12 SSIEN13 SSIEN14 SSIEN15 <After reset: H’0000>...
Page 582 CAN MODULE 13.2 CAN Module Related Registers CAN0SLIST (H'0080 100C) CAN0SLIEN (H'0080 1010) Slot 0 transmission/reception completed Data bus SSB0 35-source inputs CAN0 transmit/receive & IRB0 error interrupt request (Level) Slot 1 transmission/reception completed SSB1 IRB1 Slot 2 transmission/reception completed SSB2 IRB2 Slot 3 transmission/reception completed...
Page 583 CAN MODULE 13.2 CAN Module Related Registers CAN0SLIST (H'0080 100C) CAN0SLIEN (H'0080 1010) Slot 8 transmission/reception completed Data bus SSB8 27-source inputs To the preceding page IRB8 (Level) Slot 9 transmission/reception completed SSB9 IRB9 Slot 10 transmission/reception completed SSB10 IRB10 Slot 11 transmission/reception completed SSB11 IRB11...
Page 584 CAN MODULE 13.2 CAN Module Related Registers CAN0ERIST (H'0080 1014) CAN0ERIEN (H'0080 1015) CAN bus error occurs Data bus BEIS 19-source inputs To the preceding page BEIEN (Level) Go to error passive state EPIS EPIEN Go to bus off state EOIS EOIEN To the remaining 16-source inputs in the next page...
Page 585 CAN MODULE 13.2 CAN Module Related Registers CAN0SSIST (H'0080 1044) CAN0SSIEN (H'0080 1048) Slot 0 arbitration-lost/transmit error occurs Data bus SSIST0 16-source inputs To the preceding page SSIEN0 (Level) Slot 1 arbitration-lost/transmit error occurs SSIST1 SSIEN1 Slot 2 arbitration-lost/transmit error occurs SSIST2 SSIEN2 Slot 3 arbitration-lost/transmit error occurs...
Page 586 CAN MODULE 13.2 CAN Module Related Registers CAN0SSIST (H'0080 1044) CAN0SSIEN (H'0080 1048) Slot 8 arbitration-lost/transmit error occurs Data bus SSIST8 8-source inputs To the preceding page SSIEN8 (Level) Slot 9 arbitration-lost/transmit error occurs SSIST9 SSIEN9 Slot 10 arbitration-lost/transmit error occurs SSIST10 SSIEN10 Slot 11 arbitration-lost/transmit error occurs...
Page 587 CAN MODULE 13.2 CAN Module Related Registers CAN1SLIST (H'0080 140C) CAN1SLIEN (H'0080 1410) Slot 0 transmission/reception completed Data bus SSB0 35-source inputs CAN1 transmit/receive & IRB0 error interrupt request (Level) Slot 1 transmission/reception completed SSB1 IRB1 Slot 2 transmission/reception completed SSB2 IRB2 Slot 3 transmission/reception completed...
Page 588 CAN MODULE 13.2 CAN Module Related Registers CAN1SLIST (H'0080 140C) CAN1SLIEN (H'0080 1410) Slot 8 transmission/reception completed Data bus SSB8 27-source inputs To the preceding page IRB8 (Level) Slot 9 transmission/reception completed SSB9 IRB9 Slot 10 transmission/reception completed SSB10 IRB10 Slot 11 transmission/reception completed SSB11 IRB11...
Page 589 CAN MODULE 13.2 CAN Module Related Registers CAN1ERIST (H'0080 1414) CAN1ERIEN (H'0080 1415) CAN bus error occurs Data bus BEIS 19-source inputs To the preceding page BEIEN (Level) Go to error passive state EPIS EPIEN Go to bus off state EOIS EOIEN To the remaining 16-source inputs in the next page...
Page 590 CAN MODULE 13.2 CAN Module Related Registers CAN1SSIST (H'0080 1444) CAN1SSIEN (H'0080 1488) Slot 0 arbitration-lost/transmit error occurs Data bus SSIST0 16-source inputs To the preceding page SSIEN0 (Level) Slot 1 arbitration-lost/transmit error occurs SSIST1 SSIEN1 Slot 2 arbitration-lost/transmit error occurs SSIST2 SSIEN2 Slot 3 arbitration-lost/transmit error occurs...
Page 591 CAN MODULE 13.2 CAN Module Related Registers CAN1SSIST (H'0080 1444) CAN1SSIEN (H'0080 1488) Slot 8 arbitration-lost/transmit error occurs Data bus SSIST8 8-source inputs To the preceding page SSIEN8 (Level) Slot 9 arbitration-lost/transmit error occurs SSIST9 SSIEN9 Slot 10 arbitration-lost/transmit error occurs SSIST10 SSIEN10 Slot 11 arbitration-lost/transmit error occurs...
Page 592: Can Cause Of Error Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.9 CAN Cause of Error Registers CAN0 Cause of Error Register (CAN0EF) <Address: H’0080 1017> CAN1 Cause of Error Register (CAN1EF) <Address: H’0080 1417> BITE STFE FORME CRCE ACKE <After reset: H’00> Bit Name Function 0–1 No function assigned.
Page 593: Can Mode Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.10 CAN Mode Registers CAN0 Mode Register (CAN0MOD) <Address: H’0080 1018> CAN1 Mode Register (CAN1MOD) <Address: H’0080 1418> CMOD <After reset: H’00> Bit Name Function 0–5 No function assigned. Fix to "0". 6–7 CMOD 00: Normal mode CAN operation mode select bit...
Page 594: Can Dma Transfer Request Select Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.11 CAN DMA Transfer Request Select Registers CAN0 DMA Transfer Request Select Register (CAN0DMARQ) <Address: H’0080 1019> CDMSEL1 CDMSEL0 <After reset: H’00> Bit Name Function 0–5 No function assigned. Fix to "0". CDMSEL1 0: Slot 1 transmission failed CAN DMA1 transfer request source select bit 1: Slot 14 transmission/reception completed...
Page 595: Can Mask Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.12 CAN Mask Registers CAN0 Global Mask Register Standard ID0 (C0GMSKS0) <Address: H’0080 1028> CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0) <Address: H’0080 1030> CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) <Address: H’0080 1038>...
Page 596 CAN MODULE 13.2 CAN Module Related Registers CAN0 Global Mask Register Extended ID0 (C0GMSKE0) <Address: H’0080 102A> CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) <Address: H’0080 1032> CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) <Address: H’0080 103A> CAN1 Global Mask Register Extended ID0 (C1GMSKE0) <Address: H’0080 142A>...
Page 597 CAN MODULE 13.2 CAN Module Related Registers CAN0 Global Mask Register Extended ID2 (C0GMSKE2) <Address: H’0080 102C> CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2) <Address: H’0080 1034> CAN0 Local Mask Register B Extended ID2 (C0LMSKBE2) <Address: H’0080 103C> CAN1 Global Mask Register Extended ID2 (C1GMSKE2) <Address: H’0080 142C>...
Page 598 CAN MODULE 13.2 CAN Module Related Registers Slot 0 Slot 1 Slots controlled by the global mask register Slot 2 Slot 13 Slot controlled by local mask register A Slot 14 Slot controlled by local mask register B Slot 15 Figure 13.2.14 Relationship between the Mask Registers and the Controlled Slots Mask bit value 0: The received message and slot IDs are...
Page 599: Can Single-Shot Mode Control Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.13 CAN Single-Shot Mode Control Registers CAN0 Single-Shot Mode Control Register (CAN0SSMODE) <Address: H’0080 1040> CAN1 Single-Shot Mode Control Register (CAN1SSMODE) <Address: H’0080 1440> SSCNT0 SSCNT1 SSCNT2 SSCNT3 SSCNT4 SSCNT5 SSCNT6 SSCNT7 SSCNT8 SSCNT9 SSCNT10 SSCNT11 SSCNT12 SSCNT13 SSCNT14 SSCNT15 <After reset: H’0000>...
Page 600: Can Message Slot Control Registers
CAN MODULE 13.2 CAN Module Related Registers 13.2.14 CAN Message Slot Control Registers CAN0 Message Slot 0 Control Register (C0MSL0CNT) <Address: H’0080 1050> CAN0 Message Slot 1 Control Register (C0MSL1CNT) <Address: H’0080 1051> CAN0 Message Slot 2 Control Register (C0MSL2CNT) <Address: H’0080 1052>...
Page 601 CAN MODULE 13.2 CAN Module Related Registers (b8) b7(b15) TRSTAT TRFIN <After reset: H’00> Bit Name Function 0: Do not use the message slot as transmit slot Transmit request bit 1: Use the message slot as transmit slot 0: Do not use the message slot as receive slot Receive request bit 1: Use the message slot as receive slot 0: Transmit/receive data frame...
Page 602 CAN MODULE 13.2 CAN Module Related Registers (2) RR (Receive Request) bit (Bit 1) To use the message slot as a receive slot, set this bit to "1". To use the message slot as a data frame or remote frame transmit slot, set this bit to "0". If TR (Transmit Request) bit and RR (Receive Request) bit both are set to "1", device operation is undefined.
Page 603 CAN MODULE 13.2 CAN Module Related Registers (7) TRSTAT (Transmit/Receive Status) bit (Bit 6) This bit indicates that the CAN module is sending or receiving and is accessing the message slot. This bit is set to "1" when the CAN module is accessing, and set to "0" when not accessing. •...
Page 604: Can Message Slots
CAN MODULE 13.2 CAN Module Related Registers 13.2.15 CAN Message Slots CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) <Address: H’0080 1100> CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0) <Address: H’0080 1110> CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0) <Address: H’0080 1120> CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0) <Address: H’0080 1130>...
Page 605 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1) <Address: H’0080 1101> CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1) <Address: H’0080 1111> CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1) <Address: H’0080 1121> CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1) <Address: H’0080 1131>...
Page 606 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) <Address: H’0080 1102> CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0) <Address: H’0080 1112> CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0) <Address: H’0080 1122> CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0) <Address: H’0080 1132>...
Page 607 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1) <Address: H’0080 1103> CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1) <Address: H’0080 1113> CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1) <Address: H’0080 1123> CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1) <Address: H’0080 1133>...
Page 608 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) <Address: H’0080 1104> CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2) <Address: H’0080 1114> CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2) <Address: H’0080 1124> CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2) <Address: H’0080 1134>...
Page 609 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data Length Register (C0MSL0DLC) <Address: H’0080 1105> CAN0 Message Slot 1 Data Length Register (C0MSL1DLC) <Address: H’0080 1115> CAN0 Message Slot 2 Data Length Register (C0MSL2DLC) <Address: H’0080 1125> CAN0 Message Slot 3 Data Length Register (C0MSL3DLC) <Address: H’0080 1135>...
Page 610 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 0 (C0MSL0DT0) <Address: H’0080 1106> CAN0 Message Slot 1 Data 0 (C0MSL1DT0) <Address: H’0080 1116> CAN0 Message Slot 2 Data 0 (C0MSL2DT0) <Address: H’0080 1126> CAN0 Message Slot 3 Data 0 (C0MSL3DT0) <Address: H’0080 1136>...
Page 611 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 1 (C0MSL0DT1) <Address: H’0080 1107> CAN0 Message Slot 1 Data 1 (C0MSL1DT1) <Address: H’0080 1117> CAN0 Message Slot 2 Data 1 (C0MSL2DT1) <Address: H’0080 1127> CAN0 Message Slot 3 Data 1 (C0MSL3DT1) <Address: H’0080 1137>...
Page 612 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 2 (C0MSL0DT2) <Address: H’0080 1108> CAN0 Message Slot 1 Data 2 (C0MSL1DT2) <Address: H’0080 1118> CAN0 Message Slot 2 Data 2 (C0MSL2DT2) <Address: H’0080 1128> CAN0 Message Slot 3 Data 2 (C0MSL3DT2) <Address: H’0080 1138>...
Page 613 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 3 (C0MSL0DT3) <Address: H’0080 1109> CAN0 Message Slot 1 Data 3 (C0MSL1DT3) <Address: H’0080 1119> CAN0 Message Slot 2 Data 3 (C0MSL2DT3) <Address: H’0080 1129> CAN0 Message Slot 3 Data 3 (C0MSL3DT3) <Address: H’0080 1139>...
Page 614 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 4 (C0MSL0DT4) <Address: H’0080 110A> CAN0 Message Slot 1 Data 4 (C0MSL1DT4) <Address: H’0080 111A> CAN0 Message Slot 2 Data 4 (C0MSL2DT4) <Address: H’0080 112A> CAN0 Message Slot 3 Data 4 (C0MSL3DT4) <Address: H’0080 113A>...
Page 615 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 5 (C0MSL0DT5) <Address: H’0080 110B> CAN0 Message Slot 1 Data 5 (C0MSL1DT5) <Address: H’0080 111B> CAN0 Message Slot 2 Data 5 (C0MSL2DT5) <Address: H’0080 112B> CAN0 Message Slot 3 Data 5 (C0MSL3DT5) <Address: H’0080 113B>...
Page 616 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 6 (C0MSL0DT6) <Address: H’0080 110C> CAN0 Message Slot 1 Data 6 (C0MSL1DT6) <Address: H’0080 111C> CAN0 Message Slot 2 Data 6 (C0MSL2DT6) <Address: H’0080 112C> CAN0 Message Slot 3 Data 6 (C0MSL3DT6) <Address: H’0080 113C>...
Page 617 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Data 7 (C0MSL0DT7) <Address: H’0080 110D> CAN0 Message Slot 1 Data 7 (C0MSL1DT7) <Address: H’0080 111D> CAN0 Message Slot 2 Data 7 (C0MSL2DT7) <Address: H’0080 112D> CAN0 Message Slot 3 Data 7 (C0MSL3DT7) <Address: H’0080 113D>...
Page 618 CAN MODULE 13.2 CAN Module Related Registers CAN0 Message Slot 0 Timestamp (C0MSL0TSP) <Address: H’0080 110E> CAN0 Message Slot 1 Timestamp (C0MSL1TSP) <Address: H’0080 111E> CAN0 Message Slot 2 Timestamp (C0MSL2TSP) <Address: H’0080 112E> CAN0 Message Slot 3 Timestamp (C0MSL3TSP) <Address: H’0080 113E>...
Page 619: Can Protocol
CAN MODULE 13.3 CAN Protocol 13.3 CAN Protocol 13.3.1 CAN Protocol Frames There are four types of frames that are handled by CAN protocol: (1) Data frame (2) Remote frame (3) Error frame (4) Overload frame Frames are separated from each other by an interframe space. Data frame Standard format 0–64...
Page 620: Data Formats During Can Transmission/Reception
CAN MODULE 13.3 CAN Protocol Error frame 6–12 Error flag Error delimiter Interframe space or overload flag Overload frame 6–12 Overload flag Interframe space or overload flag Overload delimiter Interframe space For the case of an error active state 0– SOF of the next frame Bus idle Intermission...
Page 621: Can Controller Error States
CAN MODULE 13.3 CAN Protocol 13.3.3 CAN Controller Error States The CAN controller assumes one of the following three error states depending on the transmit error and receive error counter values. (1) Error active state • This is a state where almost no errors have occurred. •...
Page 622: Initializing The Can Module
CAN MODULE 13.4 Initializing the CAN Module 13.4 Initializing the CAN Module 13.4.1 Initializing the CAN Module Before performing communication, set up the CAN module as described below. (1) Selecting pin functions The CAN transmit data output pin (CTX) and CAN data receive input pin (CRX) are shared with input/output ports.
Page 623 CAN MODULE 13.4 Initializing the CAN Module 1 Bit Synchronization Propagation Segment Phase Segment1 Phase Segment2 Segment Sampling Point • This diagram shows the bit timing in cases where one bit consists of 8 Tq's. • If one-time sampling is selected, the value sampled at Sampling Point (1) is assumed to be the value of the bit.
Page 624 CAN MODULE 13.4 Initializing the CAN Module Initialize the CAN module Set the Input/Output Port Operation Mode Register Set the Interrupt Controller Set interrupt priority Set the CAN Error Interrupt Request Set the CAN Slot Interrupt Enable Register Request Enable Register •...
Page 625: Transmitting Data Frames
CAN MODULE 13.5 Transmitting Data Frames 13.5 Transmitting Data Frames 13.5.1 Data Frame Transmit Procedure The following describes the procedure for transmitting data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot to be transmitted by writing H’00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register that has just been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that transmission/reception has stopped and remains idle.
Page 626: Data Frame Transmit Operation
CAN MODULE 13.5 Transmitting Data Frames Data frame transmit procedure Initialize the CAN Message Write H'00 Slot Control Register Read the CAN Message Slot Control Register Confirm that transmission is idle TRSTAT bit = 0 Set ID and data in the message slot Set the Extended ID Register Standard ID or extended ID...
Page 627: Transmit Abort Function
CAN MODULE 13.5 Transmitting Data Frames (4) Completion of data frame transmission When data frame transmission has finished, the CAN Message Slot Control Register’s TRFIN (Transmit/ Receive Finished) bit and the CAN Slot Interrupt Request Status Register are set to "1". Also, a timestamp count value at which transmission has finished is written to the CAN Message Slot Timestamp (C0MSLnTSP, C1MSLnTSP), and the transmit operation is thereby completed.
Page 628: Receiving Data Frames
CAN MODULE 13.6 Receiving Data Frames 13.6 Receiving Data Frames 13.6.1 Data Frame Receive Procedure The following describes the procedure for receiving data frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which to receive by writing H’00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register that has just been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that reception has stopped and remains idle.
Page 629: Data Frame Receive Operation
CAN MODULE 13.6 Receiving Data Frames Data frame receive procedure Initialize the CAN Message Slot Write H'00 Control Register Read the CAN Message Slot Control Register Confirm that reception is idle TRSTAT bit = 0 Set ID in the message slot Set the Extended ID Register Standard ID or extended ID Set the CAN Message Slot...
Page 630 CAN MODULE 13.6 Receiving Data Frames (2) When the receive conditions are met When the receive conditions in (1) above are met, the CAN module sets the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at the same time writing the received data to the message slot.
Page 631: Reading Out Received Data Frames
CAN MODULE 13.6 Receiving Data Frames 13.6.3 Reading Out Received Data Frames The following shows the procedure for reading out received data frames from the slot. (1) Clearing the TRFIN (Transmit/Receive Finished) bit Write H’4E, H’40 or H’00 to the CAN Message Slot Control Register (C0MSLnCNT, C1MSLnCNT) to clear the TRFIN bit to "0".
Page 632 CAN MODULE 13.6 Receiving Data Frames Reading out received data Write H'4E, H'40 or H'00 Clear the TRFIN bit to 0 Read out from the message slot Read the CAN Message Slot Control Register TRFIN bit = 0 Finished reading out received data Figure 13.6.3 Procedure for Reading Out Received Data 32180 Group User’s Manual (Rev.1.0)
Page 633: Transmitting Remote Frames
CAN MODULE 13.7 Transmitting Remote Frames 13.7 Transmitting Remote Frames 13.7.1 Remote Frame Transmit Procedure The following describes the procedure for transmitting remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot to be transmitted by writing H’00 to the register. (2) Confirming that transmission is idle Read the CAN Message Slot Control Register that has just been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that transmission/reception has stopped and remains idle.
Page 634: Remote Frame Transmit Operation
CAN MODULE 13.7 Transmitting Remote Frames Remote frame transmit procedure Initialize the CAN Message Slot Write H'00 Control Register Read the CAN Message Slot Control Register Confirm that transmission is idle TRSTAT bit = 0 Set ID in the message slot Set the Extended ID Register Standard ID or extended ID Set the CAN Message Slot...
Page 635 CAN MODULE 13.7 Transmitting Remote Frames (4) If lost in CAN bus arbitration or a CAN bus error occurs If the CAN module lost in CAN bus arbitration or a CAN bus error occurs in the middle of transmission, the CAN module clears the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit to "0".
Page 636: Reading Out Received Data Frames When Set For Remote Frame Transmission
CAN MODULE 13.7 Transmitting Remote Frames Bit arrangement in the CAN Message Slot Control Register (b8) b7(b15) TRSTAT TRFIN B'0000 0000 Store the Clear the transmit received data request B'0000 1000 B'1010 1000 B'1010 1011 B'0000 1011 Finished storing Finished storing CAN bus error the received data the received data...
Page 637 CAN MODULE 13.7 Transmitting Remote Frames (2) Reading out from the message slot Read out a message from the message slot. (3) Checking the TRFIN (Transmit/Receive Finished) bit Read the CAN Message Slot Control Register to check the TRFIN (Transmit/Receive Finished) bit. 1) If TRFIN (Transmit/Receive Finished) bit = "1"...
Page 638: Receiving Remote Frames
CAN MODULE 13.8 Receiving Remote Frames 13.8 Receiving Remote Frames 13.8.1 Remote Frame Receive Procedure The following describes the procedure for receiving remote frames. (1) Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which to receive by writing H’00 to the register. (2) Confirming that reception is idle Read the CAN Message Slot Control Register that has just been initialized and check the TRSTAT (Transmit/ Receive Status) bit to see that reception has stopped and remains idle.
Page 639: Remote Frame Receive Operation
CAN MODULE 13.8 Receiving Remote Frames Remote frame receive procedure Initialize the CAN Message Slot Write H'00 Control Register Read the CAN Message Slot Control Register Confirm that reception is idle TRSTAT bit = 0 Set ID in the message slot Standard ID or extended ID Set the Extended ID Register Write H'60...
Page 640 CAN MODULE 13.8 Receiving Remote Frames (3) When the receive conditions are met When the receive conditions in (2) above are met, the CAN module sets the CAN Message Slot Control Register’s TRSTAT (Transmit/Receive Status) bit and TRFIN (Transmit/Receive Finished) bit to "1" while at the same time writing the received data to the message slot.
Page 641 CAN MODULE 13.8 Receiving Remote Frames Bit arrangement in the CAN Message Slot Control Register (b8) b7(b15) TRSTAT TRFIN B'0000 0000 Write H'70 Write H'60 (automatic response (automatic response disabled) enabled) Clear the receive request Wait for reception B'0110 1000 B'0111 1000 Store the Store the...
Page 642: Precautions About Can Module
CAN MODULE 13.9 Precautions about CAN Module 13.9 Precautions about CAN Module • Note for cancelation of transmit and receive CAN remote frame When aborting remote frame transmission or canceling remote frame receiving, make sure that the RA (Remote Active) bit is cleared to "0" after writing "H'00" or "H'0F" to the CAN Message Slot Control Register. (1) When aborting remote frame transmission Start transmission abort Write H'00 or H'0F to...
Page 643 CAN MODULE 13.9 Precautions about CAN Module This page is blank for reasons of layout. 32180 Group User’s Manual (Rev.1.0) 13-96...
Page 644: Chapter 14 Real Time Debugger (Rtd)
CHAPTER 14 REAL TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.2 Pin Functions of the RTD 14.3 Functional Description of the RTD 14.4 Typical Connection with the Host...
Page 645 REAL TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) 14.1 Outline of the Real-Time Debugger (RTD) The Real-Time Debugger (RTD) is a serial I/O through which to read or write to any location in the entire area of the internal RAM by using commands from outside the microcomputer.
Page 646 REAL TIME DEBUGGER (RTD) 14.2 Pin Functions of the RTD 14.2 Pin Functions of the RTD Pin Functions of the RTD are shown below. Table 14.2.1 Pin Functions of the RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input...
Page 647: Outline Of The Rtd Operation
REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3 Functional Description of the RTD 14.3.1 Outline of the RTD Operation Operation of the RTD is specified by a command entered from devices external to the chip. A command is indicated by bits 16–19 (Note 1) of the RTD received data.
Page 648 REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 32 clock 32 clock 32 clock 32 clock periods periods periods periods RTDCLK RTDRXD RDR (A1) RDR (A2) RDR (A3) RTDTXD D (A1) D (A2) RTDACK 2 clock periods Note: • (An) = Specified address •...
Page 649: Operation Of The Wrr (Ram Content Forcible Rewrite)
REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.3 Operation of the WRR (RAM Content Forcible Rewrite) When the WRR (RAM content forcible rewrite) command is issued, the RTD forcibly rewrites the contents of the internal RAM without causing the CPU’s internal bus to stop. Because the RTD writes data to the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra CPU load is incurred.
Page 650: Operation Of Ver (Continuous Monitor)
REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.4 Operation of VER (Continuous Monitor) When the VER (continuous monitor) command is issued, the RTD outputs the data from the address that has been accessed by an instruction (either read or write) immediately before receiving the VER command. (LSB side) (MSB side) 19 18 17 16...
Page 651: Operation Of Rcv (Recover From Runaway)
REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 32 clock 32 clock 32 clock 32 clock periods periods periods periods RTDCLK RTDRXD RDR(A1) (Note 1) RTDTXD RTDACK D (A1) D (A1) 2 clock periods RTD interrupt request Read value Read value RTD interrupt Note 1: WRR command can also be used.
Page 652: Method For Setting A Specified Address When Using The Rtd
REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 32 clock 32 clock 32 clock 32 clock periods periods periods periods RTDCLK Bits 20-31 1 RDR(A1) RTDRXD • • • Next command following RCV command D(A1) Indeterminate data during runaway condition RTDTXD RTDACK Indeterminate value during runaway condition...
Page 653: Resetting The Rtd
REAL TIME DEBUGGER (RTD) 14.3 Functional Description of the RTD 14.3.8 Resetting the RTD The RTD is reset by applying a system reset (i.e., RESET# signal). The status of the RTD related output pins after a system reset are shown below. Table 14.3.2 RTD Pin Status after System Reset Pin Name Status...
Page 654: Typical Connection With The Host
REAL TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host 14.4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data. The clock for synchronous communication should be generated by the host. An example for connecting the RTD and host is shown below. Host M32R/ECU microprocessor...
Page 655 REAL TIME DEBUGGER (RTD) 14.4 Typical Connection with the Host This page is blank for reasons of layout. 32180 Group User’s Manual (Rev.1.0) 14-12...
Page 656: Chapter 15 External Bus Interface
CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 Outline of the External Bus Interface 15.2 External Bus Interface Related Registers 15.3 Read/Write Operations 15.4 Bus Arbitration 15.5 Typical Connection of External Extension Memory 15.6 Example of Bus Voltage Settings Using VCC-BUS...
Page 657: External Bus Interface Related Signals
EXTERNAL BUS INTERFACE 15.1 Outline of the External Bus Interface 15.1 Outline of the External Bus Interface 15.1.1 External Bus Interface Related Signals The 32180 has the external bus interface related signals described below. These signals can be used in external extension and processor modes.
Page 658 EXTERNAL BUS INTERFACE 15.1 Outline of the External Bus Interface (6) Data bus (DB0–DB15) This is the 16-bit bus used to access external devices. During external read access, data is latched from the bus synchronously with the rising edge of the read strobe. Even during 8-bit read, 16-bit data is always read in, but data only on the valid byte position is transferred into the internal circuit.
Page 659: External Bus Interface Related Registers
EXTERNAL BUS INTERFACE 15.2 External Bus Interface Related Registers 15.2 External Bus Interface Related Registers The following describes the external bus interface related registers. 15.2.1 Port Operation Mode Registers Ports P0–P4 (except P41–P43) and P224–P227 are switched for external access signal pins during external extension mode when so set by the corresponding Operation Mode Register.
Page 660 EXTERNAL BUS INTERFACE 15.2 External Bus Interface Related Registers P1 Operation Mode Register (P1MOD) <Address: H’0080 0741> P10MD P11MD P12MD P13MD P14MD P15MD P16MD P17MD <After reset: H’00> Bit Name Function P10MD 0: P10 Port P10 operation mode bit 1: DB8 P11MD 0: P11 Port P11 operation mode bit...
Page 661 EXTERNAL BUS INTERFACE 15.2 External Bus Interface Related Registers P3 Operation Mode Register (P3MOD) <Address: H’0080 0743> P30MD P31MD P32MD P33MD P34MD P35MD P36MD P37MD <After reset: H’00> Bit Name Function P30MD 0: P30 Port P30 operation mode bit 1: A15 P31MD 0: P31 Port P31 operation mode bit...
Page 662 EXTERNAL BUS INTERFACE 15.2 External Bus Interface Related Registers P7 Operation Mode Register (P7MOD) <Address: H’0080 0747> P70MD P71MD P72MD P73MD P74MD P75MD P76MD P77MD <After reset: H’00> Bit Name Function P70MD 0: P70 Port P70 operation mode bit 1: BCLK/WR# P71MD 0: P71 Port P71 operation mode bit...
Page 663: Port Peripheral Output Select Register
EXTERNAL BUS INTERFACE 15.2 External Bus Interface Related Registers 15.2.2 Port Peripheral Output Select Register To use ports P224 and P225 as external access signal pins, their pin functions must be set using the P22 Peripheral Output Select Register, because the A11 and CS2# pins and the A12 and CS3# pins are shared. P22 Peripheral Output Select Register (P22SMOD) <Address: H’0080 0776>...
Page 664: Bus Mode Control Register
EXTERNAL BUS INTERFACE 15.2 External Bus Interface Related Registers 15.2.3 Bus Mode Control Register Bus Mode Control Register (BUSMODC) <Address: H’0080 077F> BUSMOD <After reset: H’00> Bit Name Function 8–14 No function assigned. Fix to "0". BUSMOD 0: WR signal separate mode Bus mode control bit 1: Byte enable separate mode This register is used to facilitate memory connections during processor mode and external extension mode.
Page 665: Read/Write Operations
EXTERNAL BUS INTERFACE 15.3 Read/Write Operations 15.3 Read/Write Operations (1) When the Bus Mode Control Register = "0" External read/write operations are performed using the address bus, data bus and the signals CS0#–CS3#, RD#, BHW#, BLW#, WAIT# and BCLK. In the external read cycle, the RD# signal is low while BHW# and BLW# both are high, with data read in from only the necessary byte position.
Page 666 EXTERNAL BUS INTERFACE 15.3 Read/Write Operations Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 000 (zero wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read Read (1 cycle)
Page 667 EXTERNAL BUS INTERFACE 15.3 Read/Write Operations Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 010 (2 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read Read (4 cycles)
Page 668 EXTERNAL BUS INTERFACE 15.3 Read/Write Operations (2) When the Bus Mode Control Register = "1" External read/write operations are performed using the address bus, data bus and the signals CS0#–CS3#, RD#, BHE#, BLE#, WAIT# and WR#. In the external read cycle, the RD# signal is low and the BHE# or BLE# signal output for the byte position from which to read is asserted low, with data read in from only the neces- sary byte position of the bus.
Page 669 EXTERNAL BUS INTERFACE 15.3 Read/Write Operations Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 000 (zero wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read Read (1 cycle)
Page 670 EXTERNAL BUS INTERFACE 15.3 Read/Write Operations Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 010 (2 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read Read (4 cycles)
Page 671: Bus Arbitration
EXTERNAL BUS INTERFACE 15.4 Bus Arbitration 15.4 Bus Arbitration (1) When the Bus Mode Control Register = "0" When the input signal on the HREQ# pin is pulled low and the hold request is accepted, the microcomputer goes to a hold state and outputs a low from the HACK# pin. During hold state, all bus related pins are placed in the high-impedance state, allowing data to be transferred on the system bus.
Page 672 EXTERNAL BUS INTERFACE 15.4 Bus Arbitration (2) When the Bus Mode Control Register = "1" When the input signal on the HREQ# pin is pulled low and the hold request is accepted, the microcomputer goes to a hold state and outputs a low from the HACK# pin. During hold state, all bus related pins are placed in the high-impedance state, allowing data to be transferred on the system bus.
Page 673: Typical Connection Of External Extension Memory
EXTERNAL BUS INTERFACE 15.5 Typical Connection of External Extension Memory 15.5 Typical Connection of External Extension Memory (1) When the Bus Mode Control Register = "0" A typical memory connection when using external extension memory is shown in Figure 15.5.1. (External extension memory can only be used in external extension mode and processor mode.) Flash memory M32180F8...
Page 674 EXTERNAL BUS INTERFACE 15.5 Typical Connection of External Extension Memory (2) When the Bus Mode Control Register = "1" A typical memory connection when using external extension memory is shown in Figure 15.5.2. (External extension memory can only be used in external extension mode and processor mode.) Flash memory M32180F8 Memory mapping...
Page 675 EXTERNAL BUS INTERFACE 15.5 Typical Connection of External Extension Memory (3) When the Bus Mode Control Register = "1" using a combination of 8/16-bit data bus memories The diagram below shows a typical connection of external extension memory, with an 8-bit data bus memory located in the CS0 area, and a 16-bit data bus memory located in the CS1 area.
Page 676: Example Of Bus Voltage Settings Using Vcc-Bus
EXTERNAL BUS INTERFACE 15.6 Example of Bus Voltage Settings Using VCC-BUS 15.6 Example of Bus Voltage Settings Using VCC-BUS (1) When both port and memory are connected at 5 V Ports and memory can be connected with external circuits via 5 V interfaces. M32R/ECU Port VCCE...
Page 677 EXTERNAL BUS INTERFACE 15.6 Example of Bus Voltage Settings Using VCC-BUS (3) When ports and memory are connected at 5 V and 3.3 V, respectively Ports and memory can be connected with external circuits via a 5 V interface directly as is and a 3.3 V interface, respectively.
Page 678: Chapter 16 Wait Controller
CHAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller 16.2 Wait Controller Related Registers 16.3 Typical Operation of the Wait Controller...
Page 679 WAIT CONTROLLER 16.1 Outline of the Wait Controller 16.1 Outline of the Wait Controller The Wait Controller controls the number of wait states inserted in bus cycles when accessing an extended exter- nal area. The Wait Controller is outlined in the table below. Table 16.1.1 Outline of the Wait Controller Item Description...
Page 680 WAIT CONTROLLER 16.1 Outline of the Wait Controller Table 16.1.2 Number of Wait States that Can Be Set by the Wait Controller Extended External Area Address Number of Wait States Inserted CS0 area H’0010 0000 to H’001F FFFF Zero to 7 wait states set by software (external extension mode) + any number of wait states entered from the WAIT# pin H’0000 0000 to H’001F FFFF...
Page 681: Cs Area Wait Control Registers
WAIT CONTROLLER 16.2 Wait Controller Related Registers 16.2 Wait Controller Related Registers Shown below is a Wait Controller related register map. Wait Controller Related Register Map Address +0 address +1 address b7 b8 pages H'0080 0180 CS0 Area Wait Control Register CS1 Area Wait Control Register 16-4 (CS0WTCR)
Page 682 WAIT CONTROLLER 16.2 Wait Controller Related Registers Table 16.2.1 RECOV Bit and IDLE Bit Settings and the Number of Idle Cycles Inserted RECOV IDLE Read (Followed by Write) Read (Followed by Read) Write Note: • Under each of the above conditions, no recovery cycle is inserted when RECOV bit = 0, and one recovery cycle is inserted when RECOV bit = 1.
Page 683: Typical Operation Of The Wait Controller
WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller 16.3 Typical Operation of the Wait Controller The following shows a typical operation of the Wait Controller. The Wait Controller can control bus access in zero to 7 cycles. If more access cycles than that are needed, use the WAIT function in combination with the Wait Controller.
Page 684 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 000 (zero wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 685 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 686 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 111 (7 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 687 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 010 (2 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 688 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 010 (2 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 689 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 1 (with strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 690 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 1 (with recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 691 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 1 (with idle cycle) Read...
Page 692 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 0 (WR signal separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 1 (with recovery cycle) IDLE bit = 1 (with idle cycle) Read...
Page 693 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller (2) When the Bus Mode Control Register = 1 External read/write operations are performed using the address bus, data bus and the signals CS0#–CS3#, RD#, BHE#, BLE#, WAIT# and WR#. Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) Bus free state Internal bus access...
Page 694 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 000 (zero wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 695 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 696 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 111 (7 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read (8 cycles)
Page 697 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 010 (2 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 698 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 010 (2 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read (3 + n cycles)
Page 699 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 1 (with strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 700 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 1 (with recovery cycle) IDLE bit = 0 (without idle cycle) Read...
Page 701 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 0 (without recovery cycle) IDLE bit = 1 (with idle cycle) Read...
Page 702 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller Bus Mode Control Register (Note 1) BUSMOD bit = 1 (byte enable separated) CS Area Wait Control Register (Note 2) WTCSEL bit = 001 (1 wait) SWAIT bit = 0 (without strobe wait) RECOV bit = 1 (with recovery cycle) IDLE bit = 1 (with idle cycle) Read (4 cycles)
Page 703 WAIT CONTROLLER 16.3 Typical Operation of the Wait Controller This page is blank for reasons of layout. 32180 Group User’s Manual (Rev.1.0) 16-26...
Page 704: Chapter 17 Ram Backup Mode
CHAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode 17.2 Example of RAM Backup when Power is Down 17.3 Example of RAM Backup for Saving Power Consumption 17.4 Exiting RAM Backup Mode (Wakeup)
Page 705 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode 17.1 Outline of RAM Backup Mode In RAM backup mode, the contents of the internal RAM are retained while the power is turned off (power for only the RAM is on). RAM backup mode is used for the following two purposes: •...
Page 706: Normal Operating State
RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down 17.2 Example of RAM Backup when Power is Down A typical circuit for RAM backup at power outage is shown in Figure 17.2.1. The following explains how the RAM can be backed up by using this circuit as an example.
Page 707: Ram Backup State
RAM BACKUP MODE 17.2 Example of RAM Backup when Power is Down 17.2.2 RAM Backup State Figure 17.2.3 shows the power outage RAM backup state of the M32R/ECU. When the power supply goes down, the power supply monitor IC starts feeding current from the backup battery to the M32R/ECU. Also, the power supply monitor IC’s power outage detection pin outputs a low, causing the SBI# pin or ADnINi pin to go low, which generates a RAM backup signal ((a) in Figure 17.2.3).
Page 708: Example Of Ram Backup For Saving Power Consumption
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3 Example of RAM Backup for Saving Power Consumption A typical RAM backup circuit for saving the microcomputer’s power consumption is shown in Figure 17.3.1. The follow- ing explains how the RAM is backed up for the purpose of low-power operation by using this circuit as an example. DC IN Input Output...
Page 709: Ram Backup State
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption 17.3.2 RAM Backup State Figure 17.3.3 shows the RAM backup state of the M32R/ECU. Figure 17.3.4 shows a RAM backup sequence. When the external circuit outputs a low, input on the SBI# or ADnINi pin is pulled low. A low on these input pins generates a RAM backup signal (A and (a) in Figure 17.3.3).
Page 710: Precautions To Be Observed At Power-On
RAM BACKUP MODE 17.3 Example of RAM Backup for Saving Power Consumption RAM backup Power on period 5.0V or 3.3V VCCE, VREFn , AVCCn VCC-BUS,OSC-VCC VDDE Port output setting Port input Port output setting (high level) mode (high level) Port X External input signal External input signal goes low...
Page 711: Exiting Ram Backup Mode (Wakeup)
RAM BACKUP MODE 17.4 Exiting RAM Backup Mode (Wakeup) 17.4 Exiting RAM Backup Mode (Wakeup) The processing to place the M32R/ECU out of RAM backup mode and return it to normal operation mode is referred to as “wakeup” processing. Figure 17.4.1 shows an example of wakeup processing. Wakeup processing is initiated by applying a reset.
Page 712: Chapter 18 Oscillator Circuit
CHAPTER 18 OSCILLATOR CIRCUIT 18.1 Oscillator Circuit 18.2 Clock Generator Circuit...
Page 713: Example Of An Oscillator Circuit
OSCILLATOR CIRCUIT 18.1 Oscillator Circuit 18.1 Oscillator Circuit The M32R/ECU contains an oscillator circuit that supplies operating clocks for the CPU core, internal peripheral I/ O and internal memory. The frequency supplied to the clock input pin (XIN) is multiplied by 8 by an internal PLL circuit to produce the CPU clock, which is the operating clock for the CPU core and internal memory.
Page 714: Xin Oscillation Stoppage Detection Circuit
OSCILLATOR CIRCUIT 18.1 Oscillator Circuit 18.1.2 XIN Oscillation Stoppage Detection Circuit The M32R/ECU contains a detection circuit to find whether oscillation input to the PLL circuit has stopped. The PLL circuit has a characteristic that in the absence of the reference oscillation input, it oscillates with the fre- quency of its normal mode of vibration.
Page 715 OSCILLATOR CIRCUIT 18.1 Oscillator Circuit (1) XSTAT (XIN oscillation status) bit (Bit 11) 1) Conditions under which XSTAT is set to "1" XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped.
Page 716: Oscillation Drive Capability Select Function
OSCILLATOR CIRCUIT 18.1 Oscillator Circuit 18.1.3 Oscillation Drive Capability Select Function The microcomputer incorporates a four-stage drive capability select function. Once the oscillation of the oscillator circuit has stabilized, the XIN-XOUT drive capability can be lowered. The lower the drive capability, the smaller the amount of power consumption. Clock Control Register (CLKCR) <Address: H’0080 0786>...
Page 717 OSCILLATOR CIRCUIT 18.1 Oscillator Circuit • Example of correct setting XDRVP "1" If a write cycle to other area exists in this interval, settings of XDRV bits are not reflected. XDRVP "0" XDRV Set value • Settings that do not have effect XDRVP "1"...
Page 718: System Clock Output Function
OSCILLATOR CIRCUIT 18.1 Oscillator Circuit 18.1.4 System Clock Output Function A clock whose frequency is twice that of the input clock (i.e., the peripheral clock) can be output from the BCLK pin. The BCLK pin is shared with port P70. To use this pin to output the peripheral clock, set the P7 Operation Mode Register (P7MOD) bit 8 to "1".
Page 719: Clock Generator Circuit
OSCILLATOR CIRCUIT 18.2 Clock Generator Circuit 18.2 Clock Generator Circuit Supply independent clocks to the CPU and the internal peripheral circuit. CPUCLK(CPU clock) XIN pin (64MHz–80MHz) (8MHz–10MHz) BCLK(peripheral clock) (16MHz–20MHz) Figure 18.2.1 Conceptual Diagram of Clock Generation 32180 Group User's Manual (Rev.1.0) 18-8...
Page 720: Chapter 19 Jtag
CHAPTER 19 JTAG 19.1 Outline of JTAG 19.2 Configuration of the JTAG Circuit 19.3 JTAG Registers 19.4 Basic Operation of JTAG 19.5 Boundary Scan Description Language 19.6 Notes on Board Design when Connecting JTAG 19.7 Processing Pins when Not Using JTAG...
Page 721 JTAG 19.1 Outline of JTAG 19.1 Outline of JTAG The M32R/ECU contains a JTAG (Joint Test Action Group) interface compliant with IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1a-1993). This JTAG interface can be used as an input/ output path for boundary-scan test (boundary-scan path).
Page 722 JTAG 19.2 Configuration of the JTAG Circuit 19.2 Configuration of the JTAG Circuit The JTAG circuit included in the M32R/ECU consists of several circuit blocks as shown in Figure 19.2.1. • Instruction register to hold the instruction code that is fetched through the boundary-scan path •...
Page 723: Jtag Registers
JTAG 19.3 JTAG Registers 19.3 JTAG Registers 19.3.1 Instruction Register (JTAGIR) The Instruction Register is a 6-bit register to hold instruction code. This register is set in the IR path sequence. The instructions set in this register determine the data register to be selected in the subsequent DR path sequence. The initial value of this register after test is reset (to initialize the test circuit) is b’000010 (IDCODE instruction).
Page 724: Data Register
JTAG 19.3 JTAG Registers 19.3.2 Data Register (1) Boundary Scan Register (JTAGBSR) The Boundary Scan Register is a 475-bit register used to perform boundary-scan test. The bits in this register are assigned to each pin on the microcomputer. Connected between the JTDI and JTDO pins, this register is selected when issuing EXTEST or SAMPLE/ PRELOAD instruction.
Page 725: Basic Operation Of Jtag
JTAG 19.4 Basic Operation of JTAG 19.4 Basic Operation of JTAG 19.4.1 Outline of JTAG Operation The instruction and data registers basically are accessed in conjunction with the following three operations, which are performed based on the TAP Controller’s state transition. The TAP Controller changes state accord- ing to JTMS input, and generates control signals required for operation in each state.
Page 726 JTAG 19.4 Basic Operation of JTAG The state transition of the TAP Controller and the basic configuration of the JTAG related registers are shown below. Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Note: •...
Page 727: Ir Path Sequence
JTAG 19.4 Basic Operation of JTAG 19.4.2 IR Path Sequence Instruction code is set in the Instruction Register (JTAGIR) to select the data register to be accessed in the subsequent DR path sequence. The IR path sequence is performed following the procedure described below. (1) From the Run-Test/Idle state, apply JTMS = high for a period of 2 JTCK cycles to enter the Select-IR- Scan state.
Page 728: Dr Path Sequence
JTAG 19.4 Basic Operation of JTAG 19.4.3 DR Path Sequence The data register that was selected in the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it. The DR path sequence is performed following the procedure described below. (1) From the Run-Test/Idle state, apply JTMS = high for a period of 1 JTCK cycle to enter the Select-DR- Scan state.
Page 729: Inspecting And Setting Data Registers
JTAG 19.4 Basic Operation of JTAG 19.4.4 Inspecting and Setting Data Registers To inspect or set the data register, follow the procedure described below. (1) To access the test access port (JTAG) for the first time, apply a test reset (to initialize the test circuit). One of the following two methods may be used to apply a test reset: •...
Page 730: Boundary Scan Description Language
JTAG 19.5 Boundary Scan Description Language 19.5 Boundary Scan Description Language The Boundary Scan Description Language (abbreviated BSDL) is stipulated in the supplements to the Standard Test Access Port and Boundary-Scan Architecture of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL).
Page 731: Notes On Board Design When Connecting Jtag
JTAG 19.6 Notes on Board Design when Connecting JTAG 19.6 Notes on Board Design when Connecting JTAG To materialize fast and highly reliable communication with JTAG tools, make sure wiring lengths of JTAG pins are matched during board design. JTAG tool SDI connector (JTAG connector) VCCE(5V) M32R/ECU...
Page 732 JTAG 19.6 Notes on Board Design when Connecting JTAG When JTAG tool SDI connector (JTAG connector) VCCE(5V) is connected M32R/ECU Power 10KΩ 33Ω RESET (Note 1) RESET# (Note 2) 10KΩ 33Ω JTDO 10KΩ 33Ω JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω JTCK 33Ω...
Page 733: Processing Pins When Not Using Jtag
JTAG 19.7 Processing Pins when Not Using JTAG 19.7 Processing Pins when Not Using JTAG The following shows how the pins on the chip should be processed when not using JTAG tools. VCCE(5V) M32R/ECU 0–100KΩ JTDO 0–100KΩ JTDI 0–100KΩ JTMS 0–100KΩ...
Page 734: Chapter 20 Power Supply Circuit
CHAPTER 20 POWER SUPPLY CIRCUIT 20.1 Configuration of the Power Supply Circuit 20.2 Power-On Sequence 20.3 Power-Off Sequence...
Page 735 POWER SUPPLY CIRCUIT 20.1 Configuration of the Power Supply Circuit 20.1 Configuration of the Power Supply Circuit The 32180 operates with a single 5 V ± 0.5 V or 3.3 V ± 0.3 V power supply. Unless otherwise noted, 5 V ± 0.5 V and 3.3 V ± 0.3 V in this chapter are referred to simply by 5 V and 3.3 V, respectively.
Page 736: Power-On Sequence When Not Using Ram Backup
POWER SUPPLY CIRCUIT 20.2 Power-On Sequence 20.2 Power-On Sequence 20.2.1 Power-On Sequence when Not Using RAM Backup The diagram below shows a turn-on sequence of the power supply (5.0 V or 3.3 V) when not using RAM backup. VCCE,VDDE VCC-BUS, OSC-VCC AVCC VREF...
Page 737: Power-On Sequence When Using Ram Backup
POWER SUPPLY CIRCUIT 20.2 Power-On Sequence 20.2.2 Power-On Sequence when Using RAM Backup The diagram below shows a turn-on sequence of the power supply (5.0 V or 3.3 V) when using RAM backup. If VDDE is 3.0 V or more, there will be no problem even when the limitations VDDE ≥...
Page 738: Power-Off Sequence
POWER SUPPLY CIRCUIT 20.3 Power-Off Sequence 20.3 Power-Off Sequence 20.3.1 Power-Off Sequence when Not Using RAM Backup The diagram below shows a turn-off sequence of the power supply (5.0 V or 3.3 V) when not using RAM backup. VCCE, VCC-BUS, OSC-VCC AVCC VREF...
Page 739: Power-Off Sequence When Using Ram Backup
POWER SUPPLY CIRCUIT 20.3 Power-Off Sequence 20.3.2 Power-Off Sequence when Using RAM Backup The diagram below shows a turn-off sequence of the power supply (5.0 V or 3.3 V) when using RAM backup. VCCE, VCC-BUS, OSC-VCC AVCC VREF (Note 1) (Note 2) P72/HREQ# (Note 3)
Page 740 POWER SUPPLY CIRCUIT 20.3 Power-Off Sequence VCCE, VCC-BUS, OSC-VCC AVCC VREF (Note 1) (Note 2) P72/HREQ# (Note 3) RESET# (Note 4) 3.3V VDDE Note 1: Pull the HREQ# input pin low to halt the CPU at the end of the bus cycle. Or disable RAM access in software.
Page 741 POWER SUPPLY CIRCUIT 20.3 Power-Off Sequence 32180 I/O Control Circuit Internal Voltage Generator Circuit 5 V or 3.3 V Main VDC VCCE VDDE Backup Voltage Generator Circuit 5 V or 3.3 V Sub-VDC (Note 2) EXCVDD 1–10 µF Peripheral Circuit Flash Memory EXCVCC 1–10 µF...
Page 742: Chapter 21 Electrical Characteristics
CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz 21.6 Flash Memory Related Characteristics...
Page 743 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings 21.1 Absolute Maximum Ratings Absolute Maximum Ratings Symbol Parameter Test Condition Rated Value Unit VCCE Main Power Supply VCCE=OSC-VCC -0.3–6.5 OSC-VCC Clock Power Supply VCCE=OSC-VCC -0.3–6.5 VCC-BUS Bus Power Supply VCCE=OSC-VCC -0.3–6.5 VDDE RAM Power Supply VCCE=OSC-VCC -0.3–6.5 AVCC...
Page 744: Electrical Characteristics When Vcce = 5 V, F(Xin) = 10 Mhz
ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz 21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) Recommended Operating Conditions (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5 V ± 0.5 V, Ta = –40°C to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 745 ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz Symbol Parameter Rated Value Unit FP, MOD0, 1, JTMS, JTRST, JTDI, RESET 0.2VCCE Standard input for the following pins: 0.25VCCE RTDCLK, RTDRXD, SCLKI0, 1, 4, 5, RXD0–5, TCLK0–3, TIN0–33, CRX0, 1 Standard input for the following pins: DB0–15, WAIT 0.16VCCE...
Page 746: Characteristics (When Vcce = 5 V, F(Xin) = 10 Mhz)
ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz 21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) Electrical Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5 V ± 0.5 V, Ta = –40°C to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 747: A-D Conversion Characteristics (When Vcce = 5 V, F(Xin) = 10 Mhz)
ELECTRICAL CHARACTERISTICS 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz 21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) A-D Conversion Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5.12 V, Ta = –40°C to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 748: Electrical Characteristics When Vcce = 5 V, F(Xin) = 8 Mhz
ELECTRICAL CHARACTERISTICS 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz 21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) Recommended Operating Conditions (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5 V ± 0.5 V, Ta = –40°C to 125°C Unless Otherwise Noted) Symbol Parameter...
Page 749 ELECTRICAL CHARACTERISTICS 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz Symbol Parameter Rated Value Unit Input Low FP, MOD0, 1, JTMS, JTRST, JTDI, RESET 0.2VCCE Voltage Standard input for the following pins: 0.25VCCE (Note 4) RTDCLK, RTDRXD, SCLKI0, 1, 4, 5, RXD0–5, TCLK0–3, TIN0–33, CRX0, 1 Standard input for the following pins: DB0–15, WAIT 0.16VCCE...
Page 750: Characteristics (When Vcce = 5 V, F(Xin) = 8 Mhz)
ELECTRICAL CHARACTERISTICS 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz 21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) Electrical Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5 V ± 0.5 V, Ta = –40°C to 125°C Unless Otherwise Noted) Symbol Parameter...
Page 751: A-D Conversion Characteristics (When Vcce = 5 V, F(Xin) = 8 Mhz)
ELECTRICAL CHARACTERISTICS 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz 21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) A-D Conversion Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5.12 V, Ta = –40°C to 125°C Unless Otherwise Noted) Symbol Parameter...
Page 752: Electrical Characteristics When Vcce = 3.3 V, F(Xin) = 10 Mhz
ELECTRICAL CHARACTERISTICS 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz 21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) Recommended Operating Conditions (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3 V ±...
Page 753 ELECTRICAL CHARACTERISTICS 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz Symbol Parameter Rated Value Unit Input Low FP, MOD0, 1, JTMS, JTRST, JTDI, RESET 0.2VCCE Voltage Standard input for the following pins: 0.2VCCE (Note 4) RTDCLK, RTDRXD, SCLKI0, 1, 4, 5, RXD0–5, TCLK0–3, TIN0–33, CRX0, 1 Standard input for the following pins: DB0–15, WAIT 0.2VCCE...
Page 754: Characteristics (When Vcce = 3.3 V ± 0.3 V, F(Xin) = 10 Mhz)
ELECTRICAL CHARACTERISTICS 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz 21.4.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) Electrical Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3 V ± 0.3 V, Ta = –40°C to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 755: A-D Conversion Characteristics (When Vcce = 3.3 V ± 0.3 V, F(Xin) = 10 Mhz)
ELECTRICAL CHARACTERISTICS 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz 21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 10 MHz) A-D Conversion Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3 V, Ta = –40°C to 85°C Unless Otherwise Noted) Symbol Parameter...
Page 756: Electrical Characteristics When Vcce = 3.3 V, F(Xin) = 8 Mhz
ELECTRICAL CHARACTERISTICS 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz 21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V ± 0.3 V f(XIN) = 8 MHz) Recommended Operating Conditions (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3 V ±...
Page 757 ELECTRICAL CHARACTERISTICS 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz Symbol Parameter Rated Value Unit FP, MOD0, 1, JTMS, JTRST, JTDI, RESET 0.2VCCE Standard input for the following pins: 0.2VCCE RTDCLK, RTDRXD, SCLKI0, 1, 4, 5, RXD0–5, TCLK0–3, TIN0–33, CRX0, 1 Standard input for the following pins: DB0–15, WAIT 0.2VCCE...
Page 758: Characteristics (When Vcce = 3.3 V ± 0.3 V, F(Xin) = 8 Mhz)
ELECTRICAL CHARACTERISTICS 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz 21.5.2 D.C. Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) Electrical Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3 V ± 0.3 V, Ta = –40°C to 125°C Unless Otherwise Noted) Symbol Parameter...
Page 759: A-D Conversion Characteristics (When Vcce = 3.3 V ± 0.3 V, F(Xin) = 8 Mhz)
ELECTRICAL CHARACTERISTICS 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz 21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V ± 0.3 V, f(XIN) = 8 MHz) A-D Conversion Characteristics (Referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3 V, Ta = –40°C to 125°C Unless Otherwise Noted) Symbol Parameter...
Page 760: Flash Memory Related Characteristics
ELECTRICAL CHARACTERISTICS 21.6 Flash Memory Related Characteristics 21.6 Flash Memory Related Characteristics Symbol Parameter Test Condition Rated Value Unit Topr Flash Rewrite Ambient Temperature C ° cycle Flash Rewrite Durability times tPRG Program Space 1page TBERS Block Erase Time 1Block 32180 Group User's Manual (Rev.1.0) 21-19...
Page 761: Characteristics (When Vcce = 5 V)
ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) 21.7 A.C. Characteristics (when VCCE = 5 V) • The timing conditions are referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 5 V ± 0.5 V, Ta = –40°C to 125°C unless otherwise noted. •...
Page 762 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) (4) TINi (i=0–33) Symbol Parameter Rated Value Unit See Fig. 21.7.5 tc(BCLK) × tw(TINi) TINi Input Pulse Width [14] (5) Read and write timing Symbol Parameter Rated Value Unit See Figs. 21.7.6 21.7.7 21.7.8...
Page 763 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) Symbol Parameter Rated Value Unit See Figs. 21.7.6 21.7.8 21.7.9 21.7.10 tc(BCLK) td(CSL-RDL) Chip Select Delay Time before Read ( )×(1+S)-16 [93] tc(BCLK) td(CSL-BLWL) Chip Select Delay Time before Write )×(1+S)-15 [95] td(CSL-BHWL)
Page 764 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) (8) JTAG interface timing Symbol Parameter Rated Value Unit See Fig. 21.7.13 tc(JTCK) JTCK Input Cycle Time [60] tw(JTCKH) JTCK Input High Pulse Width [61] tw(JTCKL) JTCK Input Low Pulse Width [62] tsu(JTDI-JTCK) JTDI, JTMS Input Setup Time...
Page 765: Switching Characteristics
ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) 21.7.2 Switching Characteristics (1) Input/output ports Symbol Parameter Rated Value Unit See Fig. 21.7.1 td(E-P) Port Data Output Delay Time (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Parameter Rated Value...
Page 766 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) (4) Read and write timing Symbol Parameter Rated Value Unit See Figs. 21.7.6 21.7.7 21.7.8 21.7.9 tc(Xin) tc(BCLK) BCLK Output Cycle Time [16] tc(BCLK) tw(BCLKH) BCLK Output High Pulse Width [17] tc(BCLK) tw(BCLKL)
Page 767 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) Read and write timing (continued from the preceding page) Symbol Parameter Rated Value Unit See Figs. 21.7.8 21.7.9 21.7.10 td(BLWL-D) Data Output Delay Time after Write With zero wait state: 5 [52] td(BHWL-D) (byte write mode)
Page 768: Characteristics (When Vcce = 3.3 V)
ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) 21.7.3 A.C. Characteristics 0.8VCCE BCLK 0.2VCCE tsu(P-E) th(E-P) 0.8VCCE 0.8VCCE Port input 0.2VCCE 0.2VCCE td(E-P) 0.8VCCE Port output 0.2VCCE Note: • The ports listed below operate with the VCC-BUS power supply, and not with the VCCE power supply. Therefore, the reference voltage for these ports is the VCC-BUS input voltage.
Page 769 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) SBI# 0.2VCCE 0.2VCCE [13] tw(SBIL) Figure 21.7.3 SBI Timing BCLK 0.2VCC-BUS [15] td(BCLK-TOi) 0.8VCCE 0.2VCCE Figure 21.7.4 TOi Timing [14] tw(TINi) 0.8VCCE 0.8VCCE TINi 0.2VCCE 0.2VCCE Figure 21.7.5 TINi Timing 32180 Group User's Manual (Rev.1.0) 21-28...
Page 770 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) [16] tc(BCLK) [18] tw(BCLKL) 0.43VCC-BUS BCLK 0.16VCC-BUS [17] tw(BCLKH) [19] [21] td(BCLKH-A) tv(BCLKH-A) Address 0.43VCC-BUS (A11–A30) 0.16VCC-BUS [20] [22] td(BCLKH-CS) tv(BCLKH-CS) 0.43VCC-BUS 0.16VCC-BUS (Access area) [20] [22] td(BCLKH-CS) tv(BCLKH-CS) 0.43VCC-BUS (Non-access area) [23] [92]...
Page 771 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) [16] tc(BCLK) [18] tw(BCLKL) 0.43VCC-BUS BCLK 0.16VCC-BUS [17] tw(BCLKH) [20] [22] td(BCLKH-CS) tv(BCLKH-CS) [19] [21] td(BCLKH-A) tv(BCLKH-A) Address (A11–A30) 0.43VCC-BUS CS0#, CS1#, 0.16VCC-BUS CS2#, CS3# [23] [24] td(BCLKL-RDL) tv(BCLKH-RDL) 0.16VCC-BUS Data input 0.43VCC-BUS (DB0–DB15)
Page 772 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) [55] [43] tw(RDH) tw(RDL) 0.43VCC-BUS 0.16VCC-BUS [57] [56] td(BLWH-RDL) td(RDH-BLWL) td(BHWH-RDL) td(RDH-BHWL) BLW# 0.43VCC-BUS BHW# 0.16VCC-BUS [39] [41] td(A-RDL) tv(RDH-A) Address 0.43VCC-BUS (A11–A30) 0.16VCC-BUS [93] [42] td(CSL-RDL) tv(RDH-CS) 0.16VCC-BUS (Access area) [40] [42] td(CS-RDL)
Page 773 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) [51] tw(BLWL) tw(BHWL) BLW# 0.43VCC-BUS BHW# 0.16VCC-BUS [57] [56] td(BLWH-RDL) td(RDH-BLWL) td(BHWH-RDL) td(RDH-BHWL) 0.43VCC-BUS 0.16VCC-BUS [47] [49] td(A-BLWL) tv(BLWH-A) td(A-BHWL) tv(BHWH-A) Address 0.43VCC-BUS 0.16VCC-BUS (A11–A30) [95] [50] td(CSL-BLWL) tv(BLWH-CS) td(CSL-BHWL) tv(BHWH-CS) (Access area) 0.16VCC-BUS...
Page 774 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) [68] tw(WRL) 0.43VCC-BUS 0.16VCC-BUS [73] [74] td(BLEL-WRL) tv(WRH-BLEL) td(BHEL-WRL) tv(WRH-BHEL) BLE# 0.16VCC-BUS BHE# [80] [81] td(RDH-WRL) td(WRH-RDL) 0.43VCC-BUS 0.16VCC-BUS [71] [69] tv(WRH-A) td(A-WRL) Address 0.43VCC-BUS 0.16VCC-BUS (A11–A30) [96] [72] td(CSL-WRL) tv(WRH-CS) (Access area) 0.16VCC-BUS...
Page 775 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) 0.43VCC-BUS BCLK 0.16VCC-BUS [35] tsu(HREQL-BCLKH) HREQ# 0.16VCC-BUS 0.16VCC-BUS [36] th(BCLKH-HREQL) [38] tv(BCLKL-HACKL) HACK# 0.16VCC-BUS 0.16VCC-BUS [37] td(BCLKL-HACKL) Figure 21.7.11 Bus Arbitration Timing [58] [59] JTCK, JTDI 0.8VCCE 0.8VCCE JTMS, JTRST 0.2VCCE 0.2VCCE Note: •...
Page 776 ELECTRICAL CHARACTERISTICS 21.7 A.C. Characteristics (when VCCE = 5 V) [60] tc(JTCK) [61] [62] tw(JTCKH) tw(JTCKL) 0.5VCCE JTCK [63] [64] tsu(JTDI-JTCK) th(JTCK-JTDI) Data input 0.8VCCE 0.8VCCE (JTDI) 0.2VCCE 0.2VCCE JTMS [65] [66] td(JTCK-JTDOV) td(JTCK-JTDOX) Data output 0.8VCCE 0.8VCCE 0.2VCCE 0.2VCCE (JIDO) [67] tw(JTRST)
Page 777: Timing Requirements
ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) 21.8 A.C. Characteristics (when VCCE = 3.3 V) • The timing conditions are referenced to VCCE, OSC-VCC, VCC-BUS, VDDE = 3.3V ± 0.3 V, Ta = –40°C to 125°C unless otherwise noted. •...
Page 778 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) (4) TINi (i=0–33) Symbol Parameter Rated Value Unit See Fig. 21.8.5 tc(BCLK) × tw(TINi) TINi Input Pulse Width [14] (5) Read and write timing Symbol Parameter Rated Value Unit See Figs. 21.8.6 21.8.7 21.8.8...
Page 779 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) Symbol Parameter Rated Value Unit See Figs. 21.8.6 21.8.8 21.8.9 21.8.10 tc(BCLK) td(CSL-RDL) Chip Select Delay Time before Read ( )×(1+S)-16 [93] tc(BCLK) td(CSL-BLWL) Chip Select Delay Time before Write )×(1+S)-16 [95] td(CSL-BHWL)
Page 780 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) (8) JTAG interface timing Symbol Parameter Rated Value Unit See Fig. 21.8.13 tc(JTCK) JTCK Input Cycle Time [60] tw(JTCKH) JTCK Input High Pulse Width [61] tw(JTCKL) JTCK Input Low Pulse Width [62] tsu(JTDI-JTCK) JTDI, JTMS Input Setup Time...
Page 781: Switching Characteristics
ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) 21.8.2 Switching Characteristics (1) Input/output ports Symbol Parameter Rated Value Unit See Fig. 21.8.1 td(E-P) Port Data Output Delay Time (2) Serial I/O a) CSIO mode, with internal clock selected Symbol Parameter Rated Value...
Page 782 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) (4) Read and write timing Symbol Parameter Rated Value Unit See Figs. 21.8.6 21.8.7 21.8.8 21.8.9 tc(Xin) tc(BCLK) BCLK Output Cycle Time [16] tc(BCLK) tw(BCLKH) BCLK Output High Pulse Width [17] tc(BCLK) tw(BCLKL)
Page 783 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) Read and write timing (continued from the preceding page) Symbol Parameter Rated Value Unit See Figs. 21.8.8 21.8.9 21.8.10 td(BLWL-D) Data Output Delay Time after Write With zero wait state: 5 [52] td(BHWL-D) (byte write mode)
Page 784 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) 21.8.3 A.C. Characteristics 0.8VCCE BCLK 0.2VCCE tsu(P-E) th(E-P) 0.8VCCE 0.8VCCE Port input 0.2VCCE 0.2VCCE td(E-P) 0.8VCCE Port output 0.2VCCE Note: • The ports listed below operate with the VCC-BUS power supply, and not with the VCCE power supply. Therefore, the reference voltage for these ports is the VCC-BUS input voltage.
Page 785 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) SBI# 0.2VCCE 0.2VCCE [13] tw(SBIL) Figure 21.8.3 SBI Timing BCLK 0.2VCC-BUS [15] td(BCLK-TOi) 0.8VCCE 0.2VCCE Figure 21.8.4 TOi Timing [14] tw(TINi) 0.8VCCE 0.8VCCE TINi 0.2VCCE 0.2VCCE Figure 21.8.5 TINi Timing 32180 Group User's Manual (Rev.1.0) 21-44...
Page 786 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) [16] tc(BCLK) [18] tw(BCLKL) 0.43VCC-BUS BCLK 0.16VCC-BUS [17] tw(BCLKH) [19] [21] td(BCLKH-A) tv(BCLKH-A) Address 0.43VCC-BUS (A11–A30) 0.16VCC-BUS [20] [22] td(BCLKH-CS) tv(BCLKH-CS) 0.43VCC-BUS 0.16VCC-BUS (Access area) [20] [22] td(BCLKH-CS) tv(BCLKH-CS) 0.43VCC-BUS (Non-access area) [23] [92]...
Page 787 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) [16] tc(BCLK) [18] tw(BCLKL) 0.43VCC-BUS BCLK 0.16VCC-BUS [17] tw(BCLKH) [20] [22] td(BCLKH-CS) tv(BCLKH-CS) [19] [21] td(BCLKH-A) tv(BCLKH-A) Address (A11–A30) 0.43VCC-BUS CS0#, CS1#, 0.16VCC-BUS CS2#, CS3# [23] [24] td(BCLKL-RDL) tv(BCLKH-RDL) 0.16VCC-BUS Data input 0.43VCC-BUS (DB0–DB15)
Page 788 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) [55] [43] tw(RDH) tw(RDL) 0.43VCC-BUS 0.16VCC-BUS [57] [56] td(BLWH-RDL) td(RDH-BLWL) td(BHWH-RDL) td(RDH-BHWL) BLW# 0.43VCC-BUS BHW# 0.16VCC-BUS [39] [41] td(A-RDL) tv(RDH-A) Address 0.43VCC-BUS 0.16VCC-BUS (A11–A30) [93] [42] td(CSL-RDL) tv(RDH-CS) (Access area) 0.16VCC-BUS [40] [42]...
Page 789 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) [51] tw(BLWL) tw(BHWL) BLW# 0.43VCC-BUS BHW# 0.16VCC-BUS [57] [56] td(BLWH-RDL) td(RDH-BLWL) td(BHWH-RDL) td(RDH-BHWL) 0.43VCC-BUS 0.16VCC-BUS [47] [49] td(A-BLWL) tv(BLWH-A) td(A-BHWL) tv(BHWH-A) Address 0.43VCC-BUS (A11–A30) 0.16VCC-BUS [95] [50] td(CSL-BLWL) tv(BLWH-CS) td(CSL-BHWL) tv(BHWH-CS) 0.16VCC-BUS (Access area)
Page 790 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) [68] tw(WRL) 0.43VCC-BUS 0.16VCC-BUS [73] [74] td(BLEL-WRL) tv(WRH-BLEL) td(BHEL-WRL) tv(WRH-BHEL) BLE# 0.16VCC-BUS BHE# [80] [81] td(RDH-WRL) td(WRH-RDL) 0.43VCC-BUS 0.16VCC-BUS [71] [69] tv(WRH-A) td(A-WRL) Address 0.43VCC-BUS (A11–A30) 0.16VCC-BUS [96] [72] td(CSL-WRL) tv(WRH-CS) 0.16VCC-BUS (Access area)
Page 791 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) 0.43VCC-BUS BCLK 0.16VCC-BUS [35] tsu(HREQL-BCLKH) HREQ# 0.16VCC-BUS 0.16VCC-BUS [36] th(BCLKH-HREQL) [38] tv(BCLKL-HACKL) HACK# 0.16VCC-BUS 0.16VCC-BUS [37] td(BCLKL-HACKL) Figure 21.8.11 Bus Arbitration Timing [58] [59] JTCK, JTDI 0.8VCCE 0.8VCCE JTMS, JTRST 0.2VCCE 0.2VCCE Note: •...
Page 792 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) [60] tc(JTCK) [61] [62] tw(JTCKH) tw(JTCKL) 0.5VCCE JTCK [63] [64] tsu(JTDI-JTCK) th(JTCK-JTDI) Data input 0.8VCCE 0.8VCCE (JTDI) 0.2VCCE 0.2VCCE JTMS [65] [66] td(JTCK-JTDOV) td(JTCK-JTDOX) Data output 0.8VCCE 0.8VCCE 0.2VCCE 0.2VCCE (JTDO) [67] tw(JTRST)
Page 793 ELECTRICAL CHARACTERISTICS 21.8 A.C. Characteristics (when VCCE = 3.3 V) This page is blank for reasons of layout. 32180 Group User's Manual (Rev.1.0) 21-52...
Page 794: Chapter 22 Typical Characteristics
CHAPTER 22 TYPICAL CHARACTERISTICS...
Page 795: To Be Written At A Later Time
TYPICAL CHARACTERISTICS To be written at a later time. 32180 Group User's Manual (Rev.1.0) 22-2...
Page 796: Appendix 1 Mechanical Specificaitons
APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1.1 Dimensional Outline Drawing...
Page 797 MECHANICAL SPECIFICAITONS Appendix 1 Appendix 1.1 Dimensional Outline Drawing Appendix 1.1 Dimensional Outline Drawing (1) 240-pin QFP 240P6Y-A Plastic 240pin 32 × 32mm body QFP Weight(g) Lead Material EIAJ Package Code JEDEC Code QFP240-P-3232-0.50 – Cu Alloy Recommended Mount Pad Dimension in Millimeters Symbol –...
Page 798 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32180 Instruction Processing Time...
Page 799 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 32180 Instruction Processing Time Appendix 2.1 32180 Instruction Processing Time For microcomputers, the number of instruction execution cycles in the E stage (Note 1) normally represents their instruction processing time. However, depending on pipeline operation, other stages may affect the instruction processing time.
Page 800 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 32180 Instruction Processing Time The following shows the number of memory access cycles in the IF and MEM stages. Shown here are the mini- mum number of cycles required for memory access. Therefore, these values do not always reflect the number of cycles actually required for memory or bus access.
Page 801 INSTRUCTION PROCESSING TIME Appendix 2 Appendix 2.1 32180 Instruction Processing Time This page is blank for reasons of layout. Appendix 2-4 32180 Group User's Manual (Rev. 1.0)
Page 802 APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example Processing of Unused Pins...
Page 803 PROCESSING OF UNUSED PINS Appendix 3 Appendix 3.1 Example Processing of Unused Pins Appendix 3.1 Example Processing of Unused Pins An example of how to process the unused pins of the microcomputer is shown below. (1) When operating in single-chip mode Table 3.1.1 Example Processing of Unused Pins during Single-Chip Mode (Note 1) Pin Name Processing...
Page 804 PROCESSING OF UNUSED PINS Appendix 3 Appendix 3.1 Example Processing of Unused Pins (2) When operating in external extension mode Table 3.1.2 Example Processing of Unused Pins during External Extension Mode (Note 1) Pin Name Processing Input/output ports (Note 2) P61–P63, P65–P67, Set the port for input mode and pull each pin low to VSS or P74–P77, P82–P87, P93–P97,...
Page 805 PROCESSING OF UNUSED PINS Appendix 3 Appendix 3.1 Example Processing of Unused Pins (3) When operating in processor mode Table 3.1.3 Example Processing of Unused Pins during Processor Mode (Note 1) Pin Name Processing Input/output ports (Note 2) P61–P63, P65–P67, Set the port for input mode and pull each pin low to VSS or P74–P77, P82–P87, P93–P97, pull high to VCCE via a 1 kΩ-10 kΩ...
Page 806 APPENDIX 4 SUMMARY OF PRECAUTIONS Appendix 4.1 Precautions about the CPU Appendix 4.2 Precautions about the Address Space Appendix 4.3 Precautions about EIT Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory Appendix 4.5 Precautions to Be Observed after Reset Appendix 4.6 Precautions about Input/Output Ports Appendix 4.7 Precautions about the DMAC Appendix 4.8 Precautions about the Multijunction Timers...
Page 807 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.1 Precautions about the CPU Appendix 4.1 Precautions about the CPU Appendix 4.1.1 Precautions Regarding Data Transfer When transferring data, be aware that data arrangements in registers and memory are different. Data in registers Data in memory •...
Page 808 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.2 Precautions about the Address Space Appendix 4.2 Precautions about the Address Space Appendix 4.2.1 Virtual Flash Emulation Function The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H’0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units.
Page 809 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.5 Precautions To Be Observed after Reset Appendix 4.5 Precautions To Be Observed after Reset Appendix 4.5.1 Input/output Ports After reset, the microcomputer’s input/output ports are disabled against input in order to prevent current from flowing through the port.
Page 810 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.7 Precautions about the DMAC Appendix 4.7 Precautions about the DMAC Appendix 4.7.1 About Writing to the DMAC Related Registers Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0").
Page 811 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode The following describes precautions to be observed when using TOP single-shot output mode. •...
Page 812 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Enabled (by writing to the enable bit Disabled (by underflow) or by external input) Count clock Enable bit Write to the correction register Overflow occurs H'(FFF0+0014) H'FFFF H'FFFF H'FFF8 H'(FFF8-1) Indeterminate...
Page 813 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode The following describes precautions to be observed when using TOP delayed single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
Page 814 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode The following describes precautions to be observed when using TOP continuous output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
Page 815 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode The following describes precautions to be observed when using TIO delayed single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
Page 816 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.10 Precautions on Using TML Measure Input The following describes precautions to be observed when using TML measure input. • If measure event input and write to the counter occur in the same clock period, the write value is set in the counter, whereas the up-count value (before being rewritten) is latched into the measure register.
Page 817 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.11 Precautions on Using TOU PWM Output Mode The following describes precautions to be observed when using TOU PWM output mode. • If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit, the latter has priority so that count is disabled.
Page 818 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.8 Precautions about the Multijunction Timers Appendix 4.8.14 Precautions on Using TOU Single-Shot Output Mode The following describes precautions to be observed when using TOU single-shot output mode. • If the counter stops due to an underflow in the same clock period as the timer is enabled by external input, the former has priority so that the counter stops.
Page 819 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.9 Precautions about the A-D Converters Appendix 4.9 Precautions about the A-D Converters • Forcible termination during scan operation If A-D conversion is forcibly terminated by setting the A-D conversion stop bit (AD0CSTP or AD1CSTP) to "1" during scan mode operation and the A-D data register for the channel that was in the middle of conversion is accessed for read, the read value shows the last conversion result that had been transferred to the data register before the conversion was forcibly terminated.
Page 820 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.9 Precautions about the A-D Converters (a) Example for calculating the external stabilizing capacitor C1 (addition of this capacitor is recommended) Assuming the R1 in Figure 4.9.1 is infinitely large and that the current necessary to charge the internal capacitor C2 is supplied from C1, if the potential fluctuation, Vp, caused by capacitance division of C1 and C2 is to be within 0.1 LSB, then what amount of capacitance C1 should have.
Page 821 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.9 Precautions about the A-D Converters Table 4.9.1 Sampling Time (in Which C2 Needs to Be Charged) Conversion start method Conversion speed Sampling time for the first bit Sampling time for the second and subsequent bits Single mode Slow mode Normal speed...
Page 822 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.10 Precautions about Serial I/O Appendix 4.10 Precautions about Serial I/O Appendix 4.10.1 Precautions on Using CSIO Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating.
Page 823 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.10 Precautions about Serial I/O Appendix 4.10.2 Precautions on Using UART Mode • Settings of SIO Transmit/Receive Mode Register and SIO Baud Rate Register The SIO Transmit/Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register’s BRG count source select bit must always be set before the serial I/O starts operating.
Page 824 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.11 Precautions about RAM Backup Mode Appendix 4.11 Precautions about RAM Backup Mode Appendix 4.11.1 Precautions to Be Observed at Power-On When changing port X from input mode to output mode after power-on, pay attention to the following. If port X is set for output mode while no data is set in the Port X Data Register, the port’s initial output level is instable.
Page 825 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.12 Precautions about JTAG Appendix 4.12 Precautions about JTAG Appendix 4.12.1 Notes on Board Design when Connecting JTAG To materialize fast and highly reliable communication with JTAG tools, make sure wiring lengths of JTAG pins are matched during board design.
Page 826 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.12 Precautions about JTAG When JTAG tools SDI connector (JTAG connector) VCCE(5V) connected M32R/ECU Power 10KΩ 33Ω RESET (Note 1) RESET# (Note 2) 10KΩ 33Ω JTDO 10KΩ 33Ω JTDI 10KΩ 33Ω JTMS 10KΩ 33Ω JTCK 33Ω...
Page 827 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.12 Precautions about JTAG Appendix 4.12.2 Processing Pins when Not Using JTAG The following shows how the pins on the chip should be processed when not using JTAG tools. VCCE(5V) M32R/ECU 0–100KΩ JTDO 0–100KΩ JTDI 0–100KΩ...
Page 828 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise Appendix 4.13 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise. The cor- rective measures described here are theoretically effective for noise, but require that the application system incorporating those measures be fully evaluated before it can actually be put to use.
Page 829 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise (2) Wiring of clock input/output pins Use as much thick and short wiring as possible for connections to the clock input/output pins. When connecting a capacitor to the oscillator, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible (within 20 mm).
Page 830 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise (3) Wiring of the VCNT pin Use as much thick and short wiring as possible for connections to the VCNT pin. When connecting a capacitor to VCNT, make sure its grounding lead wire and the OSC-VSS pin on the microcomputer are connected in the shortest distance possible.
Page 831 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0.1 µF between the VSS and VCC lines. At this time, make sure the require- ments described below are met.
Page 832 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it unsusceptible to influences from other signals. (1) Avoidance from large-current signal lines Signal lines that conduct a large current exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer (especially the oscillator and VCNT pin) as...
Page 833 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise (2) Avoiding effects of rapidly level-changing signal lines Locate signal lines whose levels change rapidly as far away from the oscillator as possible. Also, make sure the rapidly level-changing signal lines will not intersect the clock-related signal lines and other noise-sensi- tive signal lines.
Page 834 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise (3) Protection against signal lines that are the source of strong noise Do not use any pin that will probably be subject to strong noise for an adjacent port near the oscillator and VCNT pins.
Page 835 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for input) Method for limiting the effect of noise in input mode Adjacent pin/peripheral pin (set for output) Method for limiting the effect of noise in output mode Adjacent pin/peripheral pin (set for input)
Page 836 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise Appendix 4.13.5 Processing Input/Output Ports For input/output ports, take the appropriate measures in both hardware and software following the procedure described below. Hardware measures • Insert resistors of 100Ω or more in series to the input/output ports. Software measures •...
Page 837 SUMMARY OF PRECAUTIONS Appendix 4 Appendix 4.13 Precautions about Noise This page is blank for reasons of layout. Appendix 4-32 32180 Group User's Manual (Rev. 1.0)
Page 838 Mitsubishi 32-Bit RISC Single-Chip Microcomputers USER’S MANUAL 32180 Group Rev.1.0 All Rights Reserved. No part of this manual may be reproduced or distributed in any form or by any means without the written permission of Mitsubishi. ©2003 MITSUBISHI ELECTRIC CORPORATION...
Page 839 User’s Manual 32180 Group New publication, effective Jan. 2003. © 2003 MITSUBISHI ELECTRIC CORPORATION. Specifications subject to change without notice.

Renesas M32R/ECU Series User Manual

Chapter 1 Overview

Chapter 2 Cpu

Chapter 3 Address Space

Chapter 4 Eit

Chapter 5 Interrupt Controller (Icu)

Chapter 6 Internal Memory

Chapter 7 Reset

Chapter 8 Input/Output Ports and Pin Functions

Chapter 9 Dmac

Chapter 10 Multijunction Timers

Chapter 11 A-D Converters

Chapter 12 Serial I/O

Chapter 13 Can Module

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Summary of Contents for Renesas M32R/ECU Series