Renesas M32R/ECU Series User Manual page 666

15
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 000 (zero wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Read
Write
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Note: • When zero wait state is selected, assertion of WAIT# is not accepted.
Figure 15.3.2 Read/Write Timing (for Zero Wait Access)
Read (1 cycle)
BCLK
A11–A30
CS0#–CS3#
RD#
BHW#, BLW#
"H"
DB0–DB15
WAIT#
Write (1 cycle)
BCLK
A11–A30
CS0#–CS3#
RD#
"H"
BHW#, BLW#
DB0–DB15
WAIT#
EXTERNAL BUS INTERFACE
(Don't Care)
(Don't Care)
15-11
15.3 Read/Write Operations
32180 Group User's Manual (Rev.1.0)