Renesas M32R/ECU Series User Manual page 221

9
The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the
DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as
those to set the transfer size and the source/destination address directions.
[DMnCNT0 Register]
(1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0)
When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting
this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode.
In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control
is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer
Count Register counts in free-run mode, during which time transfer operation is continued until the transfer enable
bit is reset to "0" (to disable transfer). In ring buffer mode, no interrupt is generated at completion of DMA transfer.
(2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1)
This flag is set to "1" when a DMA transfer request occurs, and is cleared to "0" when the transfer for that
transfer request is completed. Reading this flag helps to know DMA transfer requests on each channel.
Writing "0" to this bit clears the generated DMA transfer request. Writing "1" has no effect; the bit retains the
value it had before the write.
If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been
set to "1", the next DMA transfer request is not accepted until the transfer being performed on that channel is
completed.
(3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2–3)
These bits select the cause or source of DMA transfer request on each DMA channel.
(4) TENLn (DMAn Transfer Enable) bit (Bit 4)
Setting this bit to "1" enables transfer, and the channel is made ready for DMA transfer. When all transfers on
that channel are completed (i.e., the Transfer Counter Register underflows), the bit is cleared to "0".
Setting this bit to "0" disables transfer. However, if a transfer request has already been accepted, transfers
on that channel are not disabled until after the requested transfer is completed.
(5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5)
This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer).
The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1".
(6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6)
This bit selects the direction in which the source address changes. This mode can be selected from two
choices: Address fixed or Address incremental.
(7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7)
This bit selects the direction in which the destination address changes. This mode can be selected from two
choices: Address fixed or Address incremental.
[DMnCNT1 Register]
(1) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12–15)
These bits select the cause or source of extended DMA transfer request on each DMA channel.
Note: • The extended DMA transfer request sources selected by the REQESELn (Extended DMAn
Transfer Request Source Select) bits have no effect unless the "Extended" DMA transfer re-
quest source is selected with the DMA Channel Control Register's DMA Request Source Se-
lect (REQSLn) bits.
9.2 DMAC Related Registers
9-16
32180 Group User's Manual (Rev.1.0)
DMAC