Renesas M32R/ECU Series User Manual page 93

4
3) Inexact Exception (IXCT)
The exception occurs when the operation result differs from a result led out with an infinite range of
precision. The following table shows the operation results and the respective conditions in which each
IXCT occurs.
Table 4.2.3 Operation Results when an IXCT Occurred
Occurrence Condition
Overflow occurs in OVF masked
condition
Rounding occurs
Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0"
Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1"
4) Zero Division Exception (DIV0)
The exception occurs when a finite nonzero value is divided by zero. The following table shows the
operation results when a DIV0 is occurs.
Table 4.2.4 Operation Results When a DIV0 Occurred
Dividend
Nonzero finite value
Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0"
Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1"
Please note that the DIV0 EIT processing does not occur in the following conditions.
Table 4.2.5 Cases in Which No DIV0 Occur
0
Infinity
When the DIV0 EIT processing is masked
+-Infinity (Sign is derived by exclusive
ORing the signs of the divisor and
dividend.)
Dividend
An invalid operation exception occurs
No exceptions occur (with the result = "Infinity")
Operation Result (Content of the Destination Register)
When the IXCT EIT processing for is
masked (Note 1)
Reference OVF operation results
Rounded value
Operation Result (Content of the Destination Register)
(Note 1)
4-4
4.2 EIT Events
When the IXCT EIT processing is
executed (Note 2)
No change
No change
When the DIV0 EIT processing is
executed (Note 2)
No change
Behavior
32180 Group User's Manual (Rev.1.0)
EIT