Renesas M32R/ECU Series User Manual page 396

10
(4) Single-shot output mode (without correction function)
In single-shot output mode, the timer generates a pulse in width of (reload register set value + 1) only once
and then stops. When the timer is enabled after setting the reload register, the counter is loaded with the
content of the reload register and starts counting synchronously with the count clock. The counter counts
down and when the minimum count is reached, stops upon underflow.
The F/F output waveform in single-shot output mode is inverted at startup and upon underflow, generating a
single-shot pulse waveform in width of (reload register set value + 1) only once. An interrupt request and
DMA transfer request can be generated when the counter underflows.
(5) Continuous output mode (without correction function)
In continuous output mode, the timer counts down starting from the set value of the counter and when the
counter underflows, it is loaded with the reload register value. Thereafter, this operation is repeated each
time the counter underflows, thus generating consecutive pulses in width of (reload register set value + 1).
When the timer is enabled after setting the counter and reload register, it starts counting down from the
counter's set value synchronously with the count clock and when the minimum count is reached, generates
an underflow. This underflow causes the counter to be loaded with the content of the reload register and start
counting over again. Thereafter, this operation is repeated each time an underflow occurs. To stop the
counter, disable count by writing to the enable bit in software.
The F/F output waveform in continuous output mode is inverted at startup and upon underflow, generating a
waveform of consecutive pulses until the timer stops counting. An interrupt request and DMA transfer re-
quest can be generated each time the counter underflows.
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating. In operation mode where the F/F output
is inverted when the timer is enabled, there is also a count clock-dependent delay before the F/F output is
inverted.
F/F operation (Note 1)
Figure 10.8.2 Count Clock Dependent Delay
Write to the enable bit
BCLK
Count clock
Enable
Note 1: This applies to the case where F/F output is inverted when the timer is enabled.
10.8 TOU (Output-Related 24-Bit Timer)
Count clock period
Count clock-dependent
delay
Inverted
10-153
MULTIJUNCTION TIMERS
32180 Group User's Manual (Rev.1.0)