Renesas M32R/ECU Series User Manual page 437

10
Count clock
Enable bit
H'FFFF
Counter
H'0000
Reload 0 register
Reload 1 register
F/F output
Interrupt request
due to underflow
(Note 1)
Note 1: DMA transfer request also is generated with the same timing.
Note: • This diagram does not show detailed timing information.
Figure 10.8.18 Typical Operation in PWM Output Mode (Reload 1 Register: H'FFFF)
Enabled
(by writing to the enable bit
or by external input)
Count down from
the reload 0
register set value
Undefined
value
H'E000
H'E000
H'FFFF
Data inverted by enable
Timing at which startup requests to other timers are generated
10.8 TOU (Output-Related 24-Bit Timer)
Because the reload 1 register = H'FFFF,
a superficial underflow is generated,
causing the counter to be loaded with
Superficial
the content of the reload 0 register
Underflow
underflow
Count down from
the reload 0
register set value
H'(FFFF-1)
H'(E000-1)
Data not inverted
10-194
MULTIJUNCTION TIMERS
H'(FFFF-1)
H'(E000-1)
Data not inverted
32180 Group User's Manual (Rev.1.0)