Renesas M32R/ECU Series User Manual page 529

12
<CSIO on receive side>
Receive clock
(SCLKI)
Receive enable bit
Reception finished bit
Overrun error bit
SIO receive interrupt request
(When reception finished
interrupt is selected)
(When receive error
interrupt is selected)
: Processing by software
Note 1: Changes of the Interrupt Controller's SIO Receive Interrupt Control Register interrupt request bit
Note 2: When reception finished interrupt is enabled
Note 3: When receive error interrupt is enabled
Note 4: The receive enable bit is cleared
Note 5: The Interrupt Controller's IVECT register is read or the SIO Receive Interrupt Control Register interrupt
request bit cleared
Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred)
<CSIO on receive side>
SCLKO
RXD
Internal clock selected
Set
RXD
(Note 1)
12.4 Receive Operation in CSIO Mode
<CSIO on transmit side>
SCLKI
TXD
External clock selected
First data reception
completed
b6 b0 b7
b7
Receive buffer not read
out during this interval
Set
Reception finished
interrupt request
(Note 2)
Interrupt request accepted (Note 5)
Receive error interrupt request
(Note 3)
: Interrupt request generated
12-38
Cleared
Next data reception
completed
b6
b0
Overrun error bit cleared
(Note 4)
Interrupt request accepted (Note 5)
32180 Group User's Manual (Rev.1.0)
Serial I/O