Renesas M32R/ECU Series User Manual page 382

10
BCLK/2
TIN24(P172)
TIN25(P173)
BCLK/2
TIN26(P190)
TIN27(P191)
BCLK/2
TIN28(P192)
TIN29(P193)
Figure 10.7.1 Block Diagram of TID (Input-Related 16-Bit Timer)
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating.
BCLK
Count clock
Enable
Figure 10.7.2 Count Clock Dependent Delay
clk
Clock
PRS3
control
TIN24S
IRQ11
CLK1 CLK2
IRQ11
TIN25S
clk
Clock
PRS4
control
TIN26S
IRQ11
CLK1 CLK2
IRQ11
TIN27S
clk
Clock
PRS5
control
TIN28S
IRQ11
CLK1 CLK2
IRQ11
TIN29S
Write to the enable bit
Count clock period
10.7 TID (Input-Related 16-Bit Timer)
Output event bus 0
TID 0
Reload register
ovf
Up/down-counter
udf
TOU0_7udf
TID 1
Reload register
ovf
Up/down-counter
udf
TOU1_7udf
TID 2
Reload register
ovf
Up/down-counter
udf
TOU2_7udf
Count clock-dependent
delay
10-139
MULTIJUNCTION TIMERS
IRQ14
DMA0
S
TOU0_0–7en
IRQ15,
AD1TRG(To A-D1 converter)
DMA1
S
TOU1_0–7en
IRQ17
DMA2
S
TOU2_0–7en
32180 Group User's Manual (Rev.1.0)