Table of Contents
Advertisement
11
11.2.5 A-D Conversion Speed Control Registers
A-D0 Conversion Speed Control Register (AD0CVSCR)
A-D1 Conversion Speed Control Register (AD1CVSCR)
b8
9
10
0
0
0
b
Bit Name
8–14
No function assigned. Fix to "0".
15
ADCVSD (Note 1)
A-D conversion speed control bit
Note 1: The A-D conversion speed is determined by a combination of ADCVSD bit and A-D Single Mode Register 1's relevant bit
during single mode, or a combination of ADCVSD bit and A-D Scan Mode Register 1's relevant bit during scan mode.
The A-D Conversion Speed Control Registers control the A-D conversion speed during single and scan modes
of the A-D Converter.
11
12
13
14
ADCVSD
0
0
0
0
11.2 A-D Converter Related Registers
b15
0
Function
0: Slow mode
1: Fast mode
11-24
A-D Converters
<Address: H'0080 0087>
<Address: H'0080 0A87>
<After reset: H'00>
R
0
R
32180 Group User's Manual (Rev.1.0)
W
0
W
Hide quick links:
Advertisement
Table of Contents
