Operation Of Tml Measure Input - Renesas M32R/ECU Series User Manual

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10.6.7 Operation of TML Measure Input

(1) Outline of TML measure input
In TML measure input, when the reset input signal is deasserted, the counter starts counting up synchro-
nously with the count clock. Upon event input to measure registers 0–3, the counter value is latched into each
measure register.
A TIN interrupt request can be generated by measure signal input from an external device. However, no TML
counter overflow interrupts are available.
Count clock
Reset
H'FFFF FFFF
Counter (32-bit)
Undefined
value
H'0000 0000
Measure 0 register
TIN23 interrupt request
Measure 1 register
TIN22 interrupt request
Figure 10.6.2 Typical Operation of TML Measure Input
Measure
Enabled
event 0
(by deassertion
occurs
of reset)
H'8000 0000
Undefined H'8000 0000
Undefined
Note: • This diagram does not show detailed timing information.
10-136
MULTIJUNCTION TIMERS
10.6 TML (Input-Related 32-Bit Timer)
Measure Measure
event 0 Overflow event 0
occurs occurs
occurs
H'C000 0000
H'C000 0000
32180 Group User's Manual (Rev.1.0)
Measure
event 0
occurs
H'D000 0000
H'6000 0000
H'6000 0000
H'D000 0000