Functional Description Of The Dmac; Dma Transfer Request Sources - Renesas M32R/ECU Series User Manual

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9.3 Functional Description of the DMAC

9.3.1 DMA Transfer Request Sources

For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are
various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some
internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all
transfers on another DMA channel (cascade mode).
The causes or sources of DMA transfer requests are selected using the transfer request source select bits
REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source
select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or
sources of DMA transfer requests on each channel.
Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0
REQSL0 DMA Transfer Request Source
0 0 Software start or one DMA2
transfer completed
0 1 A-D0 conversion completed
1 0 MJT (TIO8_udf)
1 1 Extended DMA0 transfer request
source selected
REQESEL0 DMA Transfer Request Source
0000 MJT (input event bus 2)
0001 MJT (TID0_udf/ovf)
0010 CAN (CAN0_S0/S15)
0011 MJT (input event bus 1)
0100 MJT (input event bus 3)
0101 MJT (output event bus 2)
0110 MJT (output event bus 3)
0111 A-D0 conversion completed
1000 MJT (TIN0 input signal)
1001 MJT (TIO8_udf)
1010
| Settings inhibited
1111
9.3 Functional Description of the DMAC
DMA Transfer Request Generation Timing
When any data is written to the DMA0 Software Request Generation Register
(software start) or when one DMA2 transfer is completed (cascade mode)
When A-D0 conversion is completed
When MJT TIO8 underflows
The source selected by the DMA0 Channel Control Register 1 (DM0CNT1)
REQESEL0 bits (see below)
DMA Transfer Request Generation Timing
When MJT input event bus 2 signal is generated
When MJT TID0 underflow/overflow occurs
When CAN0 slot 0 transmission failed or slot 15 transmission reception finished
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
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32180 Group User's Manual (Rev.1.0)
DMAC