Renesas M32R/ECU Series User Manual page 670

15
Bus Mode Control Register (Note 1)
BUSMOD bit = 1 (byte enable separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 010 (2 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Read
Write
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Notes: • Circles in the above diagram denote the sampling timing.
• BCLK is not output.
Figure 15.3.6 Read/Write Timing (for Access with Internal 2 and External 1 Wait States)
BCLK
A11–A30
CS0#–CS3#
RD#
WR#
"H"
BHW#, BLW#
DB0–DB15
WAIT# (Don't Care)
BCLK
A11–A30
CS0#–CS3#
RD#
"H"
WR#
BHW#, BLW#
DB0–DB15
WAIT#
(Don't Care)
EXTERNAL BUS INTERFACE
Read (4 cycles)
Internal External
1 wait state
2 wait states
"H"
"L"
Write (4 cycles)
Internal External
1 wait state
2 wait states
"H"
"L"
15-15
15.3 Read/Write Operations
(Don't Care)
(Don't Care)
32180 Group User's Manual (Rev.1.0)