Renesas M32R/ECU Series User Manual page 697

16
Bus Mode Control Register (Note 1)
BUSMOD bit = 1 (byte enable separated)
CS Area Wait Control Register (Note 2)
WTCSEL bit = 010 (2 wait)
SWAIT bit = 0 (without strobe wait)
RECOV bit = 0 (without recovery cycle)
IDLE bit = 0 (without idle cycle)
Read
A11–A30
CS0#–CS3#
BHE#, BLE#
DB0–DB15
Write
A11–A30
CS0#–CS3#
BHE#, BLE#
DB0–DB15
Note 1: For details about the Bus Mode Control Register, see Section 15.2.3, "Bus Mode Control Register."
Note 2: For details about the CS Area Wait Control Register, see Section 16.2.1, "CS Area Wait Control Registers."
Notes: • Circles in the above diagram indicate the sampling timing.
• BCLK is not output.
Figure 16.3.15 Read/Write Timing (for Access with Internal 2 and External 1 Wait States)
BCLK
RD#
WR#
"H"
WAIT#
(Don't Care)
BCLK
RD#
"H"
WR#
WAIT#
(Don't Care)
16.3 Typical Operation of the Wait Controller
Read (4 cycles)
External
Internal
1 wait state
2 wait states
(Don't Care)
"H"
"L"
Write (4 cycles)
Internal External
2 wait states 1 wait state
(Don't Care)
"H"
"L"
16-20
WAIT CONTROLLER
32180 Group User's Manual (Rev.1.0)