Renesas M32R/ECU Series User Manual page 522

Mitsubishi 32-bit risc single-chip microcomputers
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12
<CSIO on transmit side>
Transmit clock
(SCLKO)
Transmit enable bit
Transmit buffer empty bit
Transmit status bit
TXD
SIO transmit interrupt request
(Note 1)
(When transmit buffer empty
interrupt is selected)
(When transmission finished
interrupt is selected) (Note 8)
Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit
Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)
Note 3: When transmission finished interrupt is enable
Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared
Note 5: A transmit interrupt request is generated when transmission is enabled.
Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the
data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.
Note 7: A transmission finished interrupt request is generated by a falling edge of the internal transfer clock pulse at which
transmission of the transmit shift register data has finished or when the transmit enable bit is cleared.
Note 8: It is inhibited to select the transmission finished interrupt when an external clock is selected.
Figure 12.3.4 Example of CSIO Transmission (Transmitted Successively)
<CSIO on transmit side>
SCLKO
TXD
Internal clock selected
Set
Write to the
transmit buffer
register
(First data)
b7
b6
(Note 2)
(Note 5)
(Note 2)
Interrupt request accepted (Note 4)
: Processing by software
12.3 Transmit Operation in CSIO Mode
<CSIO on receive side>
SCLKI
RXD
External clock selected
Write to the
transmit buffer
register
(Next data)
First data
Next data
b5
b0
b7
b6
Next data is written at a transmit
buffer empty interrupt
(Note 2)(Note 6)
(Note 3)
Interrupt request accepted (Note 4)
: Interrupt request generated
12-31
Serial I/O
(Internal transfer clock)
Cleared
b5
b0
Transmit interrupt request
(Note 3)(Note 7)
32180 Group User's Manual (Rev.1.0)

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